thumbv8m.main-none-eabi and thumbv8m.main-none-eabihf
Tier: 2
Bare-metal target for CPUs in the Mainline Armv8-M architecture family, supporting a subset of the T32 ISA.
Processors in this family include the:
See arm-none-eabi for information applicable to all
arm-none-eabi targets, in particular the difference between the eabi and
eabihf ABI.
Target maintainers
- Rust Embedded Devices Working Group Cortex-M
Team, cortex-m@teams.rust-embedded.org
Target CPU and Target Feature options
See the bare-metal Arm docs for details on how to use these flags.
Table of supported CPUs for thumbv8m.main-none-eabi
| CPU | FPU | DSP | MVE | Target CPU | Target Features | 
|---|---|---|---|---|---|
| Unspecified | No | No | No | None | None | 
| Cortex-M33 | No | No | No | cortex-m33 | +soft-float,-dsp | 
| Cortex-M33 | No | Yes | No | cortex-m33 | +soft-float | 
| Cortex-M33 | SP | No | No | cortex-m33 | -dsp | 
| Cortex-M33 | SP | Yes | No | cortex-m33 | None | 
| Cortex-M35P | No | No | No | cortex-m35p | +soft-float,-dsp | 
| Cortex-M35P | No | Yes | No | cortex-m35p | +soft-float | 
| Cortex-M35P | SP | No | No | cortex-m35p | -dsp | 
| Cortex-M35P | SP | Yes | No | cortex-m35p | None | 
| Cortex-M55 | No | Yes | No | cortex-m55 | +soft-float,-mve | 
| Cortex-M55 | DP | Yes | No | cortex-m55 | -mve | 
| Cortex-M55 | No | Yes | Int | cortex-m55 | +soft-float,-mve.fp | 
| Cortex-M55 | DP | Yes | Int | cortex-m55 | -mve.fp | 
| Cortex-M55 | DP | Yes | Int+Float | cortex-m55 | None | 
| Cortex-M85 | No | Yes | No | cortex-m85 | +soft-float,-mve | 
| Cortex-M85 | DP | Yes | No | cortex-m85 | -mve | 
| Cortex-M85 | No | Yes | Int | cortex-m85 | +soft-float,-mve.fp | 
| Cortex-M85 | DP | Yes | Int | cortex-m85 | -mve.fp | 
| Cortex-M85 | DP | Yes | Int+Float | cortex-m85 | None | 
Table of supported CPUs for thumbv8m.main-none-eabihf
| CPU | FPU | DSP | MVE | Target CPU | Target Features | 
|---|---|---|---|---|---|
| Unspecified | SP | No | No | None | None | 
| Cortex-M33 | SP | No | No | cortex-m33 | -dsp | 
| Cortex-M33 | SP | Yes | No | cortex-m33 | None | 
| Cortex-M33P | SP | No | No | cortex-m35p | -dsp | 
| Cortex-M33P | SP | Yes | No | cortex-m35p | None | 
| Cortex-M55 | DP | Yes | No | cortex-m55 | -mve | 
| Cortex-M55 | DP | Yes | Int | cortex-m55 | -mve.fp | 
| Cortex-M55 | DP | Yes | Int+Float | cortex-m55 | None | 
| Cortex-M85 | DP | Yes | No | cortex-m85 | -mve | 
| Cortex-M85 | DP | Yes | Int | cortex-m85 | -mve.fp | 
| Cortex-M85 | DP | Yes | Int+Float | cortex-m85 | None | 
Arm Cortex-M33
The target CPU is cortex-m33.
- Has optional DSP extensions
- support is controlled by the dsptarget-feature
- enabled by default with this target-cpu
 
- support is controlled by the 
- Has an optional single precision FPU
- support is enabled by default with this target-cpu
- disable support using the +soft-floatfeature (eabionly)
 
Arm Cortex-M35P
The target CPU is cortex-m35p.
- Has optional DSP extensions
- support is controlled by the dsptarget-feature
- enabled by default with this target-cpu
 
- support is controlled by the 
- Has an optional single precision FPU
- support is enabled by default with this target-cpu
- disable support using the +soft-floatfeature (eabionly)
 
Arm Cortex-M55
The target CPU is cortex-m55.
- Has DSP extensions
- support is controlled by the dsptarget-feature
- enabled by default with this target-cpu
 
- support is controlled by the 
- Has an optional double-precision FPU that also supports half-precision FP16
values
- support is enabled by default with this target-cpu
- disable support using the +soft-floatfeature (eabionly)
 
- Has optional support for M-Profile Vector Extensions
- Also known as Helium Technology
- Available with only integer support, or both integer/float support
- The appropriate feature for the MVE is either mve(integer) ormve.fp(float)
- mve.fpis enabled by default on this target CPU
- disable using -mve.fp(disable float MVE) or-mve(disable all MVE)
 
Arm Cortex-M85
The target CPU is cortex-m85.
- Has DSP extensions
- support is controlled by the dsptarget-feature
- enabled by default with this target-cpu
 
- support is controlled by the 
- Has an optional double-precision FPU that also supports half-precision FP16
values
- support is enabled by default with this target-cpu
- disable support using the +soft-floatfeature (eabionly)
 
- Has optional support for M-Profile Vector Extensions
- Also known as Helium Technology
- Available with only integer support, or both integer/float support
- The appropriate feature for the MVE is either mve(integer) ormve.fp(float)
- mve.fpis enabled by default on this target CPU
- disable using -mve.fp(disable float MVE) or-mve(disable all MVE)