From: Takashi Iwai Subject: Fix i915 HSW WARNING at S4 resume Patch-mainline: Never References: bnc#894993 Paper over the left PLL enable bits that result in unnecessary kernel warnings at PM resume. Note that the refcount check is necessary there since this code path is used in another way at initialization and otherwise it'd trigger other kernel WARNINGs. The upstream has fixed the issue along with a large code restructuring, so this is only for SLE12-SP0. Signed-off-by: Takashi Iwai --- drivers/gpu/drm/i915/intel_ddi.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -960,6 +960,24 @@ void intel_ddi_setup_hw_pll_state(struct struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe; struct intel_crtc *intel_crtc; + unsigned int val; + + /* XXX we need to clear enable bits at resume (bnc#894993) */ + if (dev_priv->ddi_plls.spll_refcount > 0) { + val = I915_READ(SPLL_CTL); + if (val & SPLL_PLL_ENABLE) + I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); + } + if (dev_priv->ddi_plls.wrpll1_refcount > 0) { + val = I915_READ(WRPLL_CTL1); + if (val & WRPLL_PLL_ENABLE) + I915_WRITE(WRPLL_CTL1, val & ~WRPLL_PLL_ENABLE); + } + if (dev_priv->ddi_plls.wrpll2_refcount > 0) { + val = I915_READ(WRPLL_CTL2); + if (val & WRPLL_PLL_ENABLE) + I915_WRITE(WRPLL_CTL2, val & ~WRPLL_PLL_ENABLE); + } dev_priv->ddi_plls.spll_refcount = 0; dev_priv->ddi_plls.wrpll1_refcount = 0;