# HG changeset patch
# User Liu, Jinsong <jinsong.liu@intel.com>
# Date 1344320197 -7200
# Node ID a5f4efac996f030ba2f572b93ddbbcd1eff5ade7
# Parent  353bc0801b11ee28855cad50ffc7b8afe0efa556
x86/MCE: remove mcg_ctl and other adjustment for future vMCE

This is a middle-work patch, preparing for the future new vMCE model.
It removes mcg_ctl, disables MCG_CTL_P, and sets bank count to 2.

Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Committed-by: Jan Beulich <jbeulich@suse.com>

Index: xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/mce.c
===================================================================
--- xen-4.1.6-testing.orig/xen/arch/x86/cpu/mcheck/mce.c
+++ xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/mce.c
@@ -846,8 +846,6 @@ void mcheck_init(struct cpuinfo_x86 *c,
 
     mctelem_init(sizeof(struct mc_info));
 
-    vmce_init(c);
-
     /* Turn on MCE now */
     set_in_cr4(X86_CR4_MCE);
 
Index: xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/mce.h
===================================================================
--- xen-4.1.6-testing.orig/xen/arch/x86/cpu/mcheck/mce.h
+++ xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/mce.h
@@ -168,8 +168,6 @@ int fill_vmsr_data(struct mcinfo_bank *m
 int inject_vmce(struct domain *d);
 int vmce_domain_inject(struct mcinfo_bank *bank, struct domain *d, struct mcinfo_global *global);
 
-extern int vmce_init(struct cpuinfo_x86 *c);
-
 static inline int mce_vendor_bank_msr(const struct vcpu *v, uint32_t msr)
 {
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
Index: xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/vmce.c
===================================================================
--- xen-4.1.6-testing.orig/xen/arch/x86/cpu/mcheck/vmce.c
+++ xen-4.1.6-testing/xen/arch/x86/cpu/mcheck/vmce.c
@@ -19,12 +19,17 @@
 #include "mce.h"
 #include "x86_mca.h"
 
-#define dom_vmce(x)   ((x)->arch.vmca_msrs)
-
-uint64_t g_mcg_cap;
+/*
+ * Emulate 2 banks for guest
+ * Bank0: reserved for 'bank0 quirk' occur at some very old processors:
+ *   1). Intel cpu whose family-model value < 06-1A;
+ *   2). AMD K7
+ * Bank1: used to transfer error info to guest
+ */
+#define GUEST_BANK_NUM 2
+#define GUEST_MCG_CAP (MCG_TES_P | MCG_SER_P | GUEST_BANK_NUM)
 
-/* Real value in physical CTL MSR */
-uint64_t h_mcg_ctl = 0UL;
+#define dom_vmce(x)   ((x)->arch.vmca_msrs)
 
 int vmce_init_msr(struct domain *d)
 {
@@ -33,7 +38,6 @@ int vmce_init_msr(struct domain *d)
         return -ENOMEM;
 
     dom_vmce(d)->mcg_status = 0x0;
-    dom_vmce(d)->mcg_ctl = ~(uint64_t)0x0;
     dom_vmce(d)->nr_injection = 0;
 
     INIT_LIST_HEAD(&dom_vmce(d)->impact_header);
@@ -52,17 +56,17 @@ void vmce_destroy_msr(struct domain *d)
 
 void vmce_init_vcpu(struct vcpu *v)
 {
-    v->arch.mcg_cap = g_mcg_cap;
+    v->arch.mcg_cap = GUEST_MCG_CAP;
 }
 
 int vmce_restore_vcpu(struct vcpu *v, uint64_t caps)
 {
-    if ( caps & ~g_mcg_cap & ~MCG_CAP_COUNT & ~MCG_CTL_P )
+    if ( caps & ~GUEST_MCG_CAP & ~MCG_CAP_COUNT & ~MCG_CTL_P )
     {
         dprintk(XENLOG_G_ERR, "%s restore: unsupported MCA capabilities"
                 " %#" PRIx64 " for d%d:v%u (supported: %#Lx)\n",
                 is_hvm_vcpu(v) ? "HVM" : "PV", caps, v->domain->domain_id,
-                v->vcpu_id, g_mcg_cap & ~MCG_CAP_COUNT);
+                v->vcpu_id, GUEST_MCG_CAP & ~MCG_CAP_COUNT);
         return -EPERM;
     }
 
@@ -175,11 +179,10 @@ int vmce_rdmsr(uint32_t msr, uint64_t *v
                    *val);
         break;
     case MSR_IA32_MCG_CTL:
-        /* Always 0 if no CTL support */
+        /* Stick all 1's when CTL support, and 0's when no CTL support */
         if ( cur->arch.mcg_cap & MCG_CTL_P )
-            *val = vmce->mcg_ctl & h_mcg_ctl;
-        mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CTL 0x%"PRIx64"\n",
-                   *val);
+            *val = ~0ULL;
+        mce_printk(MCE_VERBOSE, "MCE: rdmsr MCG_CTL 0x%"PRIx64"\n", *val);
         break;
     default:
         ret = mce_bank_msr(cur, msr) ? bank_mce_rdmsr(cur, msr, val) : 0;
@@ -287,15 +290,11 @@ int vmce_wrmsr(u32 msr, u64 val)
     struct domain_mca_msrs *vmce = dom_vmce(cur->domain);
     int ret = 1;
 
-    if ( !g_mcg_cap )
-        return 0;
-
     spin_lock(&vmce->lock);
 
     switch ( msr )
     {
     case MSR_IA32_MCG_CTL:
-        vmce->mcg_ctl = val;
         break;
     case MSR_IA32_MCG_STATUS:
         vmce->mcg_status = val;
@@ -509,31 +508,6 @@ int vmce_domain_inject(
     return inject_vmce(d);
 }
 
-int vmce_init(struct cpuinfo_x86 *c)
-{
-    u64 value;
-
-    rdmsrl(MSR_IA32_MCG_CAP, value);
-    /* For Guest vMCE usage */
-    g_mcg_cap = value & (MCG_CAP_COUNT | MCG_CTL_P | MCG_TES_P | MCG_SER_P);
-    if (value & MCG_CTL_P)
-        rdmsrl(MSR_IA32_MCG_CTL, h_mcg_ctl);
-
-    return 0;
-}
-
-static int mca_ctl_conflict(struct mcinfo_bank *bank, struct domain *d)
-{
-    if ( !bank || !d )
-        return 1;
-
-    /* Will MCE happen in host if If host mcg_ctl is 0? */
-    if ( ~d->arch.vmca_msrs->mcg_ctl & h_mcg_ctl )
-        return 1;
-
-    return 0;
-}
-
 static int is_hvm_vmce_ready(struct mcinfo_bank *bank, struct domain *d)
 {
     struct vcpu *v;
@@ -587,14 +561,6 @@ static int is_hvm_vmce_ready(struct mcin
     if (no_vmce)
         return 0;
 
-    /* Guest has different MCE ctl value setting */
-    if (mca_ctl_conflict(bank, d))
-    {
-        dprintk(XENLOG_WARNING,
-          "No vmce, guest has different mca control setting\n");
-        return 0;
-    }
-
     return 1;
 }
 
Index: xen-4.1.6-testing/xen/include/asm-x86/mce.h
===================================================================
--- xen-4.1.6-testing.orig/xen/include/asm-x86/mce.h
+++ xen-4.1.6-testing/xen/include/asm-x86/mce.h
@@ -16,7 +16,6 @@ struct bank_entry {
 struct domain_mca_msrs
 {
     /* Guest should not change below values after DOM boot up */
-    uint64_t mcg_ctl;
     uint64_t mcg_status;
     uint16_t nr_injection;
     struct list_head impact_header;
