Cleanup some APIC handling code in the HyperV shim.

Signed-off-by: K. Y. Srinivasan <ksrinivasan@novell.com>

Index: xen-4.0.2-testing/xen/arch/x86/hvm/hyperv/hv_intercept.c
===================================================================
--- xen-4.0.2-testing.orig/xen/arch/x86/hvm/hyperv/hv_intercept.c
+++ xen-4.0.2-testing/xen/arch/x86/hvm/hyperv/hv_intercept.c
@@ -252,71 +252,6 @@ hv_get_max_vcpus_supported(void)
 
 
 static inline void
-hv_read_icr(u64 *icr_content)
-{
-    unsigned long    icr_low, icr_high;
-
-    icr_low = vlapic_mmio_handler.read_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_ICR), 4, &icr_low);
-    icr_high = vlapic_mmio_handler.read_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_ICR2), 4, &icr_high);
-    *icr_content = (((u64)icr_high<< 32) | icr_low);
-
-}
-
-static inline void
-hv_read_tpr(u64 *tpr_content)
-{
-
-    vlapic_mmio_handler.read_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_TASKPRI),
-         4, (unsigned long *)&tpr_content);
-}
-
-static inline void
-hv_write_eoi(u64 msr_content)
-{
-    u32 eoi = (u32)msr_content;
-
-    vlapic_mmio_handler.write_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_EOI), 4, eoi);
-
-}
-
-static inline void
-hv_write_icr(u64 msr_content)
-{
-    u32    icr_low, icr_high;
-    icr_low = (u32)msr_content;
-    icr_high = (u32)(msr_content >> 32);
-
-    if (icr_high != 0)
-    {
-        vlapic_mmio_handler.write_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_ICR2), 4,
-        icr_high);
-    }
-    if (icr_low != 0)
-    {
-        vlapic_mmio_handler.write_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_ICR), 4,
-        icr_low);
-    }
-
-}
-
-static inline void
-hv_write_tpr(u64 msr_content)
-{
-    u32 tpr = (u32)msr_content;
-
-
-    vlapic_mmio_handler.write_handler(current,
-         (vlapic_base_address(vcpu_vlapic(current)) + APIC_TASKPRI), 4, tpr);
-
-}
-
-static inline void
 hv_hypercall_page_initialize(void *hypercall_page)
 {
     char *p;
@@ -810,21 +745,14 @@ hyperv_do_rd_msr(uint32_t idx, struct cp
         regs->edx = (u32)(0x0);
         break;
     case HV_MSR_ICR:
-        if (!hv_privilege_check(curp, HV_ACCESS_APIC_MSRS)) {
-            goto msr_read_error;
-        }
-        hv_read_icr(&msr_content);
+	regs->eax = vlapic_get_reg(vcpu_vlapic(current), APIC_ICR);
+	regs->edx = vlapic_get_reg(vcpu_vlapic(current), APIC_ICR2);
 #ifdef HV_STATS
         cur_vcpu->stats.num_icr_reads++;
 #endif
-        regs->eax = (u32)(msr_content & 0xFFFFFFFF);
-        regs->edx = (u32)(msr_content >> 32);
         break;
     case HV_MSR_TPR:
-        if (!hv_privilege_check(curp, HV_ACCESS_APIC_MSRS)) {
-            goto msr_read_error;
-        }
-        hv_read_tpr(&msr_content);
+	msr_content = vlapic_get_reg(vcpu_vlapic(current), APIC_TASKPRI);
 #ifdef HV_STATS
         cur_vcpu->stats.num_tpr_reads++;
 #endif
@@ -922,28 +850,30 @@ hyperv_do_wr_msr(uint32_t idx, struct cp
         goto msr_write_error;
 
     case HV_MSR_EOI:
-        if (!hv_privilege_check(curp, HV_ACCESS_APIC_MSRS)) {
-            goto msr_write_error;
-        }
-        hv_write_eoi(msr_content);
+	vlapic_EOI_set(vcpu_vlapic(current));
 #ifdef HV_STATS
         cur_vcpu->stats.num_eoi_writes++;
 #endif
         break;
-    case HV_MSR_ICR:
-        if (!hv_privilege_check(curp, HV_ACCESS_APIC_MSRS)) {
-            goto msr_write_error;
-        }
-        hv_write_icr(msr_content);
+    case HV_MSR_ICR: {
+	u32 eax = (u32)msr_content;
+	u32 edx = (u32)(msr_content >> 32);
+	struct vlapic *vlapic = vcpu_vlapic(current);
+	eax &= ~(1 << 12);
+	edx &= 0xff000000;
+	vlapic_set_reg(vlapic, APIC_ICR2, edx);
+	if ( vlapic_ipi(vlapic, eax, edx) == X86EMUL_OKAY )
+		vlapic_set_reg(vlapic, APIC_ICR, eax);
+	break;
+    }
+
 #ifdef HV_STATS
         cur_vcpu->stats.num_icr_writes++;
 #endif
         break;
     case HV_MSR_TPR:
-        if (!hv_privilege_check(curp, HV_ACCESS_APIC_MSRS)) {
-            goto msr_write_error;
-        }
-        hv_write_tpr(msr_content);
+	vlapic_set_reg(vcpu_vlapic(current), APIC_TASKPRI,
+			(uint8_t)msr_content);
 #ifdef HV_STATS
         cur_vcpu->stats.num_tpr_writes++;
 #endif
