--- src/pcl.c	2009-12-02 10:10:28.000000000 -0800
+++ src/pcl.c	2011-04-15 13:30:23.000000000 -0700
@@ -1163,61 +1163,71 @@ PAPI_mh_info_t sys_mem_info[5] = {
     }
    }
   ,                             // POWER6 end
-  // This section is a placeholder for Power7 data, and is currently
-  // just a copy of the Power6 data.  When Power7 goes public, this
-  // should be updated.
   {3,
    {
-    {                           // level 1 begins
-     {                          // tlb's begin
-      /// POWER7 has an ERAT (Effective to Real Address
-      /// Translation) instead of a TLB.  For the purposes of this
-      /// data, we will treat it like a TLB.
-      {PAPI_MH_TYPE_INST, 128, 2}
-      ,
-      {PAPI_MH_TYPE_DATA, 128, 128}
-      }
+    [0] = { // level 1 begins
+     .tlb = {
+       /// POWER7 has an ERAT (Effective to Real Address
+       /// Translation) instead of a TLB.  For the purposes of this
+       /// data, we will treat it like a TLB.
+       [0] = { .type = PAPI_MH_TYPE_INST,
+               .num_entries = 64, .page_size = 0, .associativity = 2 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_DATA,
+               .num_entries = 64, .page_size = 0,
+               .associativity = SHRT_MAX }
+     }
      ,
-     {                          // caches begin
-      {PAPI_MH_TYPE_INST, 65536, 128, 512, 4}
-      ,
-      {PAPI_MH_TYPE_DATA, 65536, 128, 512, 8}
-      }
+     .cache = { // level 1 caches begin
+       [0] = { .type = PAPI_MH_TYPE_INST | PAPI_MH_TYPE_PSEUDO_LRU,
+               .size = 32768, .line_size = 128, .num_lines = 64,
+               .associativity = 4 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_DATA | PAPI_MH_TYPE_WT | PAPI_MH_TYPE_LRU,
+               .size = 32768, .line_size = 128, .num_lines = 32,
+               .associativity = 8 }
      }
+    }
     ,
-    {                           // level 2 begins
-     {                          // tlb's begin
-      {PAPI_MH_TYPE_EMPTY, -1, -1}
-      ,
-      {PAPI_MH_TYPE_EMPTY, -1, -1}
-      }
+    [1] = { // level 2 begins
+     .tlb = {
+       [0] = { .type = PAPI_MH_TYPE_EMPTY, .num_entries = -1,
+               .page_size = -1, .associativity = -1 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_EMPTY, .num_entries = -1,
+               .page_size = -1, .associativity = -1 }
+     }
      ,
-     {                          // caches begin
-      {PAPI_MH_TYPE_UNIFIED, 4194304, 128, 16384, 8}
-      ,
-      {PAPI_MH_TYPE_EMPTY, -1, -1, -1, -1}
-      }
+     .cache = {
+       [0] = { .type = PAPI_MH_TYPE_UNIFIED | PAPI_MH_TYPE_PSEUDO_LRU,
+               .size = 262144, .line_size = 128, .num_lines = 256,
+               .associativity = 8 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_EMPTY, .size = -1, .line_size = -1,
+               .num_lines = -1, .associativity = -1 }
      }
+    }
     ,
-    {                           // level 3 begins
-     {                          // tlb's begin
-      {PAPI_MH_TYPE_EMPTY, -1, -1}
-      ,
-      {PAPI_MH_TYPE_EMPTY, -1, -1}
-      }
+    [2] = { // level 3 begins
+     .tlb = {
+       [0] = { .type = PAPI_MH_TYPE_EMPTY, .num_entries = -1,
+               .page_size = -1, .associativity = -1 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_EMPTY, .num_entries = -1,
+               .page_size = -1, .associativity = -1 }
+     }
      ,
-     {                          // caches begin
-      /// POWER7 has a 2 slice L3 cache.  Each slice is 16MB, so
-      /// combined they are 32MB and usable by each core.  For
-      /// this reason, we will treat it as a single 32MB cache.
-      {PAPI_MH_TYPE_UNIFIED, 33554432, 128, 262144, 16}
-      ,
-      {PAPI_MH_TYPE_EMPTY, -1, -1, -1, -1}
-      }
+     .cache = {
+       [0] = { .type = PAPI_MH_TYPE_UNIFIED | PAPI_MH_TYPE_PSEUDO_LRU,
+               .size = 4194304, .line_size = 128, .num_lines = 4096,
+               .associativity = 8 }
+       ,
+       [1] = { .type = PAPI_MH_TYPE_EMPTY, .size = -1, .line_size = -1,
+               .num_lines = -1, .associativity = -1 }
      }
-    ,
     }
-   }                            // POWER7 end
+   }
+  }						 // POWER7 end
 };
 
 #define SPRN_PVR 0x11F          /* Processor Version Register */
