From ef4d084fae9d4719bc52f97e15e41e1602e3bc6e Mon Sep 17 00:00:00 2001
From: Eugeni Dodonov <eugeni.dodonov@intel.com>
Date: Fri, 13 Apr 2012 17:08:38 -0300
Subject: drm/i915: add WRPLL divider programming bits
Git-commit: ef4d084fae9d4719bc52f97e15e41e1602e3bc6e
Patch-mainline: v3.6-rc1

Those are used to program the WRPLL dividers correctly for each gives
frequency.

Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Michal Srb <msrb@suse.com>
---
 drivers/gpu/drm/i915/i915_reg.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc1a5c6..0668815 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4191,6 +4191,10 @@
 #define  WRPLL_PLL_SELECT_SSC			(0x01<<28)
 #define  WRPLL_PLL_SELECT_NON_SCC		(0x02<<28)
 #define  WRPLL_PLL_SELECT_LCPLL_2700	(0x03<<28)
+/* WRPLL divider programming */
+#define  WRPLL_DIVIDER_REFERENCE(x)		((x)<<0)
+#define  WRPLL_DIVIDER_POST(x)			((x)<<8)
+#define  WRPLL_DIVIDER_FEEDBACK(x)		((x)<<16)
 
 /* Port clock selection */
 #define PORT_CLK_SEL_A			0x46100

