# Commit ea58a679a6190e714a592f1369b660769a48a80c
# Date 2018-01-26 14:10:21 +0000
# Author Andrew Cooper <andrew.cooper3@citrix.com>
# Committer Andrew Cooper <andrew.cooper3@citrix.com>
x86/msr: Emulation of MSR_{SPEC_CTRL,PRED_CMD} for guests

As per the spec currently available here:

https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf

MSR_ARCH_CAPABILITIES will only come into existence on new hardware, but is
implemented as a straight #GP for now to avoid being leaky when new hardware
arrives.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3032,6 +3032,22 @@ int hvm_msr_read_intercept(unsigned int 
         *msr_content = var_range_base[index];
         break;
 
+    case MSR_PRED_CMD:
+        /* Write-only */
+        goto gp_fault;
+
+    case MSR_SPEC_CTRL:
+        cpuid[2] = 0;
+        hvm_cpuid(7, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
+        if ( !(cpuid[3] & cpufeat_mask(X86_FEATURE_IBRSB)) )
+            goto gp_fault;
+        *msr_content = v->arch.spec_ctrl;
+        break;
+
+    case MSR_ARCH_CAPABILITIES:
+        /* Not implemented yet. */
+        goto gp_fault;
+
     case MSR_K8_ENABLE_C1E:
     case MSR_AMD64_NB_CFG:
          /*
@@ -3159,6 +3175,43 @@ int hvm_msr_write_intercept(unsigned int
             goto gp_fault;
         break;
 
+    case MSR_SPEC_CTRL:
+        cpuid[2] = 0;
+        hvm_cpuid(7, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
+        if ( !(cpuid[3] & cpufeat_mask(X86_FEATURE_IBRSB)) )
+            goto gp_fault; /* MSR available? */
+
+        /*
+         * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
+         * when STIBP isn't enumerated in hardware.
+         */
+
+        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+            goto gp_fault; /* Rsvd bit set? */
+
+        v->arch.spec_ctrl = msr_content;
+        break;
+
+    case MSR_PRED_CMD:
+        cpuid[2] = 0;
+        hvm_cpuid(7, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[3]);
+        hvm_cpuid(0x80000008, &cpuid[0], &cpuid[1], &cpuid[2], &cpuid[0]);
+        if ( !(cpuid[3] & cpufeat_mask(X86_FEATURE_IBRSB)) &&
+             !(cpuid[1] & cpufeat_mask(X86_FEATURE_IBPB)) )
+            goto gp_fault; /* MSR available? */
+
+        /*
+         * The only defined behaviour is when writing PRED_CMD_IBPB.  In
+         * practice, real hardware accepts any value without faulting.
+         */
+        if ( msr_content & PRED_CMD_IBPB )
+            wrmsrl(MSR_PRED_CMD, PRED_CMD_IBPB);
+        break;
+
+    case MSR_ARCH_CAPABILITIES:
+        /* Read-only */
+        goto gp_fault;
+
     case MSR_AMD64_NB_CFG:
         /* ignore the write */
         break;
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2542,6 +2542,8 @@ static int emulate_privileged_op(struct 
         msr_content = ((uint64_t)edx << 32) | eax;
         switch ( (u32)regs->ecx )
         {
+            uint32_t ebx, dummy;
+
 #ifdef CONFIG_X86_64
         case MSR_FS_BASE:
             if ( is_pv_32on64_vcpu(v) )
@@ -2666,6 +2668,41 @@ static int emulate_privileged_op(struct 
             if ( wrmsr_safe(regs->ecx, msr_content) != 0 )
                 goto fail;
             break;
+        case MSR_ARCH_CAPABILITIES:
+            /* The MSR is read-only. */
+            goto fail;
+
+        case MSR_SPEC_CTRL:
+            domain_cpuid(v->domain, 7, 0, &dummy, &dummy, &dummy, &edx);
+            if ( !(edx & cpufeat_mask(X86_FEATURE_IBRSB)) )
+                goto fail; /* MSR available? */
+
+            /*
+             * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored)
+             * when STIBP isn't enumerated in hardware.
+             */
+
+            if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+                goto fail; /* Rsvd bit set? */
+
+            v->arch.spec_ctrl = eax;
+            break;
+
+        case MSR_PRED_CMD:
+            domain_cpuid(v->domain, 7, 0, &dummy, &dummy, &dummy, &edx);
+            domain_cpuid(v->domain, 0x80000008, 0, &dummy, &ebx, &dummy,
+                         &dummy);
+            if ( !(edx & cpufeat_mask(X86_FEATURE_IBRSB)) &&
+                 !(ebx & cpufeat_mask(X86_FEATURE_IBPB)) )
+                goto fail; /* MSR available? */
+
+            /*
+             * The only defined behaviour is when writing PRED_CMD_IBPB.  In
+             * practice, real hardware accepts any value without faulting.
+             */
+            if ( eax & PRED_CMD_IBPB )
+                wrmsrl(MSR_PRED_CMD, PRED_CMD_IBPB);
+            break;
         default:
             if ( wrmsr_hypervisor_regs(regs->ecx, msr_content) == 1 )
                 break;
@@ -2699,6 +2736,8 @@ static int emulate_privileged_op(struct 
     case 0x32: /* RDMSR */
         switch ( (u32)regs->ecx )
         {
+            uint32_t edx, dummy;
+
 #ifdef CONFIG_X86_64
         case MSR_FS_BASE:
             if ( is_pv_32on64_vcpu(v) )
@@ -2756,6 +2795,21 @@ static int emulate_privileged_op(struct 
             regs->eax = (uint32_t)msr_content;
             regs->edx = (uint32_t)(msr_content >> 32);
             break;
+        case MSR_PRED_CMD:
+            /* Write-only */
+            goto fail;
+
+        case MSR_SPEC_CTRL:
+            domain_cpuid(v->domain, 7, 0, &dummy, &dummy, &dummy, &edx);
+            if ( !(edx & cpufeat_mask(X86_FEATURE_IBRSB)) )
+                goto fail;
+            regs->eax = v->arch.spec_ctrl;
+            regs->edx = 0;
+            break;
+
+        case MSR_ARCH_CAPABILITIES:
+            /* Not implemented yet. */
+            goto fail;
         default:
             if ( rdmsr_hypervisor_regs(regs->ecx, &val) )
             {
--- a/xen/include/asm-x86/domain.h
+++ b/xen/include/asm-x86/domain.h
@@ -521,6 +521,8 @@ struct arch_vcpu
     struct mapcache_vcpu mapcache;
 #endif
 
+    uint32_t spec_ctrl;
+
     uint32_t gdbsx_vcpu_event;
 
     /* A secondary copy of the vcpu time info. */
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -39,6 +39,8 @@
 #define MSR_PRED_CMD			0x00000049
 #define PRED_CMD_IBPB			(_AC(1, UL) << 0)
 
+#define MSR_ARCH_CAPABILITIES		0x0000010a
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_PERFCTR1		0x000000c2
