From: Wei Wang <wei.w.wang@intel.com>
Date: Tue, 7 Nov 2017 16:39:49 +0800
Subject: [PATCH] i386/kvm: MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD

CPUID(EAX=0X7,ECX=0).EDX[26]/[27] indicates the support of
MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD. Expose the CPUID
to the guest. Also add the support of transferring the MSRs during live
migration.

Signed-off-by: Wei Wang <wei.w.wang@intel.com>
---

Index: xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/cpuid.c
===================================================================
--- xen-4.2.5-testing.orig/tools/qemu-xen-dir-remote/target-i386/cpuid.c
+++ xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/cpuid.c
@@ -1164,6 +1164,12 @@ void cpu_x86_cpuid(CPUX86State *env, uin
             *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
             *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
             *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
+        } else if (count == 0) {
+            host_cpuid(index, 0, eax, ebx, ecx, edx);
+            *eax = 0;
+            *ebx = 0;
+            *ecx = 0;
+            *edx = env->cpuid_features | *edx;
         } else {
             *eax = 0;
             *ebx = 0;
Index: xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/cpu.h
===================================================================
--- xen-4.2.5-testing.orig/tools/qemu-xen-dir-remote/target-i386/cpu.h
+++ xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/cpu.h
@@ -283,6 +283,7 @@
 #define MSR_IA32_APICBASE_BSP           (1<<8)
 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
+#define MSR_IA32_SPEC_CTRL              0x00000048
 #define MSR_IA32_TSCDEADLINE            0x6e0
 
 #define MSR_MTRRcap			0xfe
@@ -438,6 +439,9 @@
 #define CPUID_SVM_PAUSEFILTER  (1 << 10)
 #define CPUID_SVM_PFTHRESHOLD  (1 << 12)
 
+#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26)
+#define CPUID_7_0_EDX_PRED_CMD      (1U << 27)
+
 #define CPUID_VENDOR_INTEL_1 0x756e6547 /* "Genu" */
 #define CPUID_VENDOR_INTEL_2 0x49656e69 /* "ineI" */
 #define CPUID_VENDOR_INTEL_3 0x6c65746e /* "ntel" */
@@ -771,6 +775,7 @@ typedef struct CPUX86State {
     XMMReg ymmh_regs[CPU_NB_REGS];
 
     uint64_t xcr0;
+    uint64_t spec_ctrl;
 } CPUX86State;
 
 CPUX86State *cpu_x86_init(const char *cpu_model);
Index: xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/kvm.c
===================================================================
--- xen-4.2.5-testing.orig/tools/qemu-xen-dir-remote/target-i386/kvm.c
+++ xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/kvm.c
@@ -59,6 +59,7 @@ const KVMCapabilityInfo kvm_arch_require
 
 static bool has_msr_star;
 static bool has_msr_hsave_pa;
+static bool has_msr_spec_ctrl;
 static bool has_msr_tsc_deadline;
 static bool has_msr_async_pf_en;
 static bool has_msr_misc_enable;
@@ -570,6 +571,9 @@ static int kvm_get_supported_msrs(KVMSta
                     has_msr_hsave_pa = true;
                     continue;
                 }
+                if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {
+                    has_msr_spec_ctrl = true;
+                    break;
                 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
                     has_msr_tsc_deadline = true;
                     continue;
@@ -898,6 +902,9 @@ static int kvm_put_msrs(CPUState *env, i
         kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
                           env->msr_ia32_misc_enable);
     }
+    if (has_msr_spec_ctrl) {
+        kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
+    }
 #ifdef TARGET_X86_64
     if (lm_capable_kernel) {
         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1183,6 +1190,9 @@ static int kvm_get_msrs(CPUState *env)
     if (ret < 0) {
         return ret;
     }
+    if (has_msr_spec_ctrl) {
+        kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
+    }
 
     for (i = 0; i < ret; i++) {
         switch (msrs[i].index) {
@@ -1239,6 +1249,9 @@ static int kvm_get_msrs(CPUState *env)
         case MSR_IA32_MISC_ENABLE:
             env->msr_ia32_misc_enable = msrs[i].data;
             break;
+        case MSR_IA32_SPEC_CTRL:
+            env->spec_ctrl = msrs[i].data;
+            break;
         default:
             if (msrs[i].index >= MSR_MC0_CTL &&
                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
Index: xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/machine.c
===================================================================
--- xen-4.2.5-testing.orig/tools/qemu-xen-dir-remote/target-i386/machine.c
+++ xen-4.2.5-testing/tools/qemu-xen-dir-remote/target-i386/machine.c
@@ -346,6 +346,23 @@ static const VMStateDescription vmstate_
     }
 };
 
+static bool spec_ctrl_needed(void *opaque)
+{
+    CPUState *env = opaque;
+
+    return env->spec_ctrl != 0;
+}
+
+static const VMStateDescription vmstate_spec_ctrl = {
+    .name = "cpu/spec_ctrl",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(spec_ctrl, CPUState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_cpu = {
     .name = "cpu",
     .version_id = CPU_SAVE_VERSION,
@@ -462,6 +479,9 @@ static const VMStateDescription vmstate_
         }, {
             .vmsd = &vmstate_msr_ia32_misc_enable,
             .needed = misc_enable_needed,
+        }, {
+            .vmsd = &vmstate_spec_ctrl,
+            .needed = spec_ctrl_needed,
         } , {
             /* empty */
         }
