From 6639484ddaf6707b41082c9fa9ca9af342df6402 Mon Sep 17 00:00:00 2001
From: Libin Yang <libin.yang@linux.intel.com>
Date: Fri, 29 Jan 2016 20:39:09 +0800
Subject: [PATCH] ALSA: hda - disable dynamic clock gating on Broxton before reset
Git-commit: 6639484ddaf6707b41082c9fa9ca9af342df6402
Patch-mainline: 4.5-rc2
References: bsc#966137

On Broxton, to make sure the reset controller works properly,
MISCBDCGE bit (bit 6) in CGCTL (0x48) of PCI configuration space
need be cleared before reset and set back to 1 after reset.
Otherwise, it may prevent the CORB/RIRB logic from being reset.

Signed-off-by: Libin Yang <libin.yang@linux.intel.com>
Cc: <stable@vger.kernel.org> # v4.4+
Signed-off-by: Takashi Iwai <tiwai@suse.de>

---
 sound/pci/hda/hda_intel.c |   15 +++++++++++++++
 1 file changed, 15 insertions(+)

--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -361,6 +361,8 @@ enum {
 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 
 /* Defines for Intel SCH HDA snoop control */
+#define INTEL_HDA_CGCTL	 0x48
+#define INTEL_HDA_CGCTL_MISCBDCGE        (0x1 << 6)
 #define INTEL_SCH_HDA_DEVC      0x78
 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 
@@ -1250,10 +1252,17 @@ static void bxt_reduce_dma_latency(struc
 static void azx_init_chip(struct azx *chip, int full_reset)
 {
 	struct pci_dev *pci = chip->pci;
+	u32 val;
 
 	if (chip->initialized)
 		return;
 
+	if (IS_BROXTON(pci)) {
+		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
+		val = val & ~INTEL_HDA_CGCTL_MISCBDCGE;
+		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
+	}
+
 	/* reset controller */
 	azx_reset(chip, full_reset);
 
@@ -1273,6 +1282,12 @@ static void azx_init_chip(struct azx *ch
 	if (IS_BROXTON(pci))
 		bxt_reduce_dma_latency(chip);
 
+	if (IS_BROXTON(pci)) {
+		pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val);
+		val = val | INTEL_HDA_CGCTL_MISCBDCGE;
+		pci_write_config_dword(pci, INTEL_HDA_CGCTL, val);
+	}
+
 	chip->initialized = 1;
 }
 
