# Commit de17162cafd27f2865a3102a2ec0f386a02ed03d # Date 2024-03-01 20:14:19 +0000 # Author Andrew Cooper # Committer Andrew Cooper x86/cpu-policy: Allow for levelling of VERW side effects MD_CLEAR and FB_CLEAR need OR-ing across a migrate pool. Allow this, by having them unconditinally set in max, with the host values reflected in default. Annotate the bits as having special properies. Signed-off-by: Andrew Cooper Reviewed-by: Roger Pau Monné --- a/xen/arch/x86/cpu-policy.c +++ b/xen/arch/x86/cpu-policy.c @@ -476,6 +476,19 @@ static void __init guest_common_feature_ */ if ( boot_cpu_has(X86_FEATURE_IBRSB) ) __set_bit(X86_FEATURE_IBPB, fs); + + if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL ) + { + /* + * These bits indicate that the VERW instruction may have gained + * scrubbing side effects. With pooling, they mean "you might migrate + * somewhere where scrubbing is necessary", and may need exposing on + * unaffected hardware. This is fine, because the VERW instruction + * has been around since the 286. + */ + __set_bit(X86_FEATURE_MD_CLEAR, fs); + __set_bit(X86_FEATURE_FB_CLEAR, fs); + } } static void __init calculate_pv_max_policy(void) --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -107,6 +107,7 @@ /* CPUID level 0x00000007:0.edx */ #define cpu_has_srbds_ctrl boot_cpu_has(X86_FEATURE_SRBDS_CTRL) +#define cpu_has_md_clear boot_cpu_has(X86_FEATURE_MD_CLEAR) #define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) #define cpu_has_arch_caps boot_cpu_has(X86_FEATURE_ARCH_CAPS) --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -254,7 +254,7 @@ XEN_CPUFEATURE(IBPB_RET, 8*32+30) / XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A AVX512 Neural Network Instructions */ XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A AVX512 Multiply Accumulation Single Precision */ XEN_CPUFEATURE(SRBDS_CTRL, 9*32+ 9) /* MSR_MCU_OPT_CTRL and RNGDS_MITG_DIS. */ -XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*A VERW clears microarchitectural buffers */ +XEN_CPUFEATURE(MD_CLEAR, 9*32+10) /*!A VERW clears microarchitectural buffers */ XEN_CPUFEATURE(TSX_FORCE_ABORT, 9*32+13) /* MSR_TSX_FORCE_ABORT.RTM_ABORT */ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel) */ XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ @@ -298,7 +298,7 @@ XEN_CPUFEATURE(DOITM, 16*32 XEN_CPUFEATURE(SBDR_SSDP_NO, 16*32+13) /*A No Shared Buffer Data Read or Sideband Stale Data Propagation */ XEN_CPUFEATURE(FBSDP_NO, 16*32+14) /*A No Fill Buffer Stale Data Propagation */ XEN_CPUFEATURE(PSDP_NO, 16*32+15) /*A No Primary Stale Data Propagation */ -XEN_CPUFEATURE(FB_CLEAR, 16*32+17) /*A Fill Buffers cleared by VERW */ +XEN_CPUFEATURE(FB_CLEAR, 16*32+17) /*!A Fill Buffers cleared by VERW */ XEN_CPUFEATURE(FB_CLEAR_CTRL, 16*32+18) /* MSR_OPT_CPU_CTRL.FB_CLEAR_DIS */ XEN_CPUFEATURE(RRSBA, 16*32+19) /*! Restricted RSB Alternative */ XEN_CPUFEATURE(BHI_NO, 16*32+20) /*A No Branch History Injection */