From 83d83392e3e5432a9240e6b060119f01d27f2a30 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@linux.intel.com>
Date: Mon, 30 Nov 2015 16:23:43 +0200
Subject: [PATCH] drm/i915: Fix vbt PWM max setup for CTG
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Git-commit: 83d83392e3e5432a9240e6b060119f01d27f2a30
Patch-mainline: 4.5-rc1
References: bsc#1005545

CTG uses hrawclk for backlight, so calculate the max based on that
instead of cdclk.

Fixes: aa17cdb4f836 ("drm/i915: initialize backlight max from VBT")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1448893432-6978-3-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>

---
 drivers/gpu/drm/i915/intel_panel.c |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -1344,13 +1344,19 @@ static u32 i9xx_hz_to_pwm(struct intel_c
 
 /*
  * Gen4: This value represents the period of the PWM stream in display core
- * clocks multiplied by 128.
+ * clocks ([DevCTG] HRAW clocks) multiplied by 128.
+ *
  */
 static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
 {
 	struct drm_device *dev = connector->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	int clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
+	int clock;
+
+	if (IS_G4X(dev_priv))
+		clock = MHz(intel_hrawclk(dev));
+	else
+		clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
 
 	return clock / (pwm_freq_hz * 128);
 }
