From: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Subject: powerpc/pseries: add Gen3 definitions for PCIE link speed
Patch-mainline: v3.14-rc5
Git-commit: 49d9684a54d21930372b7fb0d3d7b5617f621706
References: bnc#863310, fate#315275, LTC#104113
X-Patchwork-Id: 312071

Summary:     ## powerpc: add little-endian support
Description: ## Add little-endian support for POWER8.

Upstream-Description:

    Rev3 of the PCI Express Base Specification defines a Supported Link
    Speeds Vector where the bit definitions within this field are:
    
    Bit 0 - 2.5 GT/s
    Bit 1 - 5.0 GT/s
    Bit 2 - 8.0 GT/s
    
    This vector definition is used by the platform firmware to export the
    maximum and current link speeds of the PCI bus via the
    "ibm,pcie-link-speed-stats" device-tree property.
    
    This patch updates pseries_root_bridge_prepare() to detect Gen3
    speed buses (defined by 0x04).
    
    Signed-off-by: Kleber Sacilotto de Souza <klebers@linux.vnet.ibm.com>

Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Acked-by: Torsten Duwe <duwe@suse.de>
---
arch/powerpc/platforms/pseries/pci.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/platforms/pseries/pci.c b/arch/powerpc/platforms/pseries/pci.c
index a6f7a14..c413ec1 100644
--- a/arch/powerpc/platforms/pseries/pci.c
+++ b/arch/powerpc/platforms/pseries/pci.c
@@ -144,6 +144,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 	case 0x02:
 		bus->max_bus_speed = PCIE_SPEED_5_0GT;
 		break;
+	case 0x04:
+		bus->max_bus_speed = PCIE_SPEED_8_0GT;
+		break;
 	default:
 		bus->max_bus_speed = PCI_SPEED_UNKNOWN;
 		break;
@@ -156,6 +159,9 @@ int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
 	case 0x02:
 		bus->cur_bus_speed = PCIE_SPEED_5_0GT;
 		break;
+	case 0x04:
+		bus->cur_bus_speed = PCIE_SPEED_8_0GT;
+		break;
 	default:
 		bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
 		break;
