Index: include/elf/avr.h
===================================================================
--- include/elf/avr.h.orig	2014-12-01 14:28:49.000000000 +0100
+++ include/elf/avr.h	2014-12-01 14:29:02.000000000 +0100
@@ -41,13 +41,14 @@
 #define E_AVR_MACH_AVR5     5
 #define E_AVR_MACH_AVR51   51
 #define E_AVR_MACH_AVR6     6 
-#define E_AVR_MACH_XMEGA1 101
-#define E_AVR_MACH_XMEGA2 102
-#define E_AVR_MACH_XMEGA3 103
-#define E_AVR_MACH_XMEGA4 104
-#define E_AVR_MACH_XMEGA5 105
-#define E_AVR_MACH_XMEGA6 106
-#define E_AVR_MACH_XMEGA7 107
+#define E_AVR_MACH_AVRTINY 100
+#define E_AVR_MACH_XMEGA1  101
+#define E_AVR_MACH_XMEGA2  102
+#define E_AVR_MACH_XMEGA3  103
+#define E_AVR_MACH_XMEGA4  104
+#define E_AVR_MACH_XMEGA5  105
+#define E_AVR_MACH_XMEGA6  106
+#define E_AVR_MACH_XMEGA7  107
 
 /* Relocations.  */
 START_RELOC_NUMBERS (elf_avr_reloc_type)
@@ -81,6 +82,12 @@ START_RELOC_NUMBERS (elf_avr_reloc_type)
      RELOC_NUMBER (R_AVR_8_LO8,                27)
      RELOC_NUMBER (R_AVR_8_HI8,                28)
      RELOC_NUMBER (R_AVR_8_HLO8,               29)
+     RELOC_NUMBER (R_AVR_DIFF8,                30)
+     RELOC_NUMBER (R_AVR_DIFF16,               31)
+     RELOC_NUMBER (R_AVR_DIFF32,               32)
+     RELOC_NUMBER (R_AVR_LDS_STS_16,           33)
+     RELOC_NUMBER (R_AVR_PORT6,                34)
+     RELOC_NUMBER (R_AVR_PORT5,                35)
 END_RELOC_NUMBERS (R_AVR_max)
 
 #endif /* _ELF_AVR_H */
Index: include/elf/common.h
===================================================================
--- include/elf/common.h.orig	2014-12-01 14:28:49.000000000 +0100
+++ include/elf/common.h	2014-12-01 14:29:02.000000000 +0100
@@ -192,7 +192,7 @@
 #define EM_MN10300	 89	/* Matsushita MN10300 */
 #define EM_MN10200	 90	/* Matsushita MN10200 */
 #define EM_PJ		 91	/* picoJava */
-#define EM_OPENRISC	 92	/* OpenRISC 32-bit embedded processor */
+#define EM_OR1K		 92	/* OpenRISC 1000 32-bit embedded processor */
 #define EM_ARC_A5	 93	/* ARC Cores Tangent-A5 */
 #define EM_XTENSA	 94	/* Tensilica Xtensa Architecture */
 #define EM_VIDEOCORE	 95	/* Alphamosaic VideoCore processor */
@@ -408,6 +408,9 @@
 
 #define EM_ADAPTEVA_EPIPHANY   0x1223  /* Adapteva's Epiphany architecture.  */
 
+/* Old constant that might be in use by some software. */
+#define EM_OPENRISC		EM_OR1K
+
 /* See the above comment before you add a new EM_* value here.  */
 
 /* Values for e_version.  */
@@ -959,6 +962,7 @@
 #define AT_BASE_PLATFORM 24		/* String identifying real platform,
 					   may differ from AT_PLATFORM.  */
 #define AT_RANDOM	25		/* Address of 16 random bytes.  */
+#define AT_HWCAP2	26		/* Extension of AT_HWCAP.  */
 #define AT_EXECFN	31		/* Filename of executable.  */
 /* Pointer to the global system page used for system calls and other
    nice things.  */
Index: include/elf/mips.h
===================================================================
--- include/elf/mips.h.orig	2014-12-01 14:28:49.000000000 +0100
+++ include/elf/mips.h	2014-12-01 14:35:17.000000000 +0100
@@ -89,7 +89,14 @@ START_RELOC_NUMBERS (elf_mips_reloc_type
   RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49)
   RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50)
   RELOC_NUMBER (R_MIPS_GLOB_DAT, 51)
-  FAKE_RELOC (R_MIPS_max, 52)
+  /* Space to grow */
+  RELOC_NUMBER (R_MIPS_PC21_S2, 60)
+  RELOC_NUMBER (R_MIPS_PC26_S2, 61)
+  RELOC_NUMBER (R_MIPS_PC18_S3, 62)
+  RELOC_NUMBER (R_MIPS_PC19_S2, 63)
+  RELOC_NUMBER (R_MIPS_PCHI16, 64)
+  RELOC_NUMBER (R_MIPS_PCLO16, 65)
+  FAKE_RELOC (R_MIPS_max, 66)
   /* These relocs are used for the mips16.  */
   FAKE_RELOC (R_MIPS16_min, 100)
   RELOC_NUMBER (R_MIPS16_26, 100)
@@ -239,6 +246,12 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* -mips64r2 code.  */
 #define E_MIPS_ARCH_64R2        0x80000000
 
+/* -mips32r6 code.  */
+#define E_MIPS_ARCH_32R6        0x90000000
+
+/* -mips64r6 code.  */
+#define E_MIPS_ARCH_64R6        0xa0000000
+
 /* The ABI of the file.  Also see EF_MIPS_ABI2 above. */
 #define EF_MIPS_ABI		0x0000F000
 
@@ -275,6 +288,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_OCTEON	0x008b0000
 #define E_MIPS_MACH_XLR     	0x008c0000
 #define E_MIPS_MACH_OCTEON2	0x008d0000
+#define E_MIPS_MACH_OCTEON3	0x008e0000
 #define E_MIPS_MACH_5400	0x00910000
 #define E_MIPS_MACH_5900	0x00920000
 #define E_MIPS_MACH_5500	0x00980000
@@ -429,6 +443,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 /* Runtime procedure descriptor table exception information (ucode) ??? */
 #define SHT_MIPS_PDR_EXCEPTION	0x70000029
 
+/* ABI related flags section.  */
+#define SHT_MIPS_ABIFLAGS	0x7000002a
 
 /* A section of type SHT_MIPS_LIBLIST contains an array of the
    following structure.  The sh_link field is the section index of the
@@ -594,6 +610,9 @@ extern void bfd_mips_elf32_swap_reginfo_
 
 /* .MIPS.options section.  */
 #define PT_MIPS_OPTIONS		0x70000002
+
+/* Records ABI related flags.  */
+#define PT_MIPS_ABIFLAGS	0x70000003
 
 /* Processor specific dynamic array tags.  */
 
@@ -1049,6 +1068,58 @@ typedef struct
   bfd_vma ri_gp_value;
 } Elf64_Internal_RegInfo;
 
+/* ABI Flags structure version 0.  */
+
+typedef struct
+{
+  /* Version of flags structure.  */
+  unsigned char version[2];
+  /* The level of the ISA: 1-5, 32, 64.  */
+  unsigned char isa_level[1];
+  /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise.  */
+  unsigned char isa_rev[1];
+  /* The size of general purpose registers.  */
+  unsigned char gpr_size[1];
+  /* The size of co-processor 1 registers.  */
+  unsigned char cpr1_size[1];
+  /* The size of co-processor 2 registers.  */
+  unsigned char cpr2_size[1];
+  /* The floating-point ABI.  */
+  unsigned char fp_abi[1];
+  /* Processor-specific extension.  */
+  unsigned char isa_ext[4];
+  /* Mask of ASEs used.  */
+  unsigned char ases[4];
+  /* Mask of general flags.  */
+  unsigned char flags1[4];
+  unsigned char flags2[4];
+} Elf_External_ABIFlags_v0;
+
+typedef struct
+{
+  /* Version of flags structure.  */
+  unsigned short version;
+  /* The level of the ISA: 1-5, 32, 64.  */
+  unsigned char isa_level;
+  /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise.  */
+  unsigned char isa_rev;
+  /* The size of general purpose registers.  */
+  unsigned char gpr_size;
+  /* The size of co-processor 1 registers.  */
+  unsigned char cpr1_size;
+  /* The size of co-processor 2 registers.  */
+  unsigned char cpr2_size;
+  /* The floating-point ABI.  */
+  unsigned char fp_abi;
+  /* Processor-specific extension.  */
+  unsigned long isa_ext;
+  /* Mask of ASEs used.  */
+  unsigned long ases;
+  /* Mask of general flags.  */
+  unsigned long flags1;
+  unsigned long flags2;
+} Elf_Internal_ABIFlags_v0;
+
 typedef struct
 {
   /* The hash value computed from the name of the corresponding
@@ -1089,6 +1160,12 @@ extern void bfd_mips_elf64_swap_reginfo_
 extern void bfd_mips_elf64_swap_reginfo_out
   (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *);
 
+/* MIPS ELF flags swapping routines.  */
+extern void bfd_mips_elf_swap_abiflags_v0_in
+  (bfd *, const Elf_External_ABIFlags_v0 *, Elf_Internal_ABIFlags_v0 *);
+extern void bfd_mips_elf_swap_abiflags_v0_out
+  (bfd *, const Elf_Internal_ABIFlags_v0 *, Elf_External_ABIFlags_v0 *);
+
 /* Masks for the info work of an ODK_EXCEPTIONS descriptor.  */
 #define OEX_FPU_MIN	0x1f	/* FPEs which must be enabled.  */
 #define OEX_FPU_MAX	0x1f00	/* FPEs which may be enabled.  */
@@ -1126,6 +1203,57 @@ extern void bfd_mips_elf64_swap_reginfo_
 /* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor.  */
 #define OHWA0_R4KEOP_CHECKED	0x00000001
 #define OHWA0_R4KEOP_CLEAN	0x00000002
+
+/* Values for the xxx_size bytes of an ABI flags structure.  */
+
+#define AFL_REG_NONE	     0x00	/* No registers.  */
+#define AFL_REG_32	     0x01	/* 32-bit registers.  */
+#define AFL_REG_64	     0x02	/* 64-bit registers.  */
+#define AFL_REG_128	     0x03	/* 128-bit registers.  */
+
+/* Masks for the ases word of an ABI flags structure.  */
+
+#define AFL_ASE_DSP          0x00000001 /* DSP ASE.  */
+#define AFL_ASE_DSPR2        0x00000002 /* DSP R2 ASE.  */
+#define AFL_ASE_EVA          0x00000004 /* Enhanced VA Scheme.  */
+#define AFL_ASE_MCU          0x00000008 /* MCU (MicroController) ASE.  */
+#define AFL_ASE_MDMX         0x00000010 /* MDMX ASE.  */
+#define AFL_ASE_MIPS3D       0x00000020 /* MIPS-3D ASE.  */
+#define AFL_ASE_MT           0x00000040 /* MT ASE.  */
+#define AFL_ASE_SMARTMIPS    0x00000080 /* SmartMIPS ASE.  */
+#define AFL_ASE_VIRT         0x00000100 /* VZ ASE.  */
+#define AFL_ASE_MSA          0x00000200 /* MSA ASE.  */
+#define AFL_ASE_MIPS16       0x00000400 /* MIPS16 ASE.  */
+#define AFL_ASE_MICROMIPS    0x00000800 /* MICROMIPS ASE.  */
+#define AFL_ASE_XPA          0x00001000 /* XPA ASE.  */
+#define AFL_ASE_MASK         0x00001fff /* All ASEs.  */
+
+/* Values for the isa_ext word of an ABI flags structure.  */
+
+#define AFL_EXT_XLR           1  /* RMI Xlr instruction.  */
+#define AFL_EXT_OCTEON2       2  /* Cavium Networks Octeon2.  */
+#define AFL_EXT_OCTEONP       3  /* Cavium Networks OcteonP.  */
+#define AFL_EXT_LOONGSON_3A   4  /* Loongson 3A.  */
+#define AFL_EXT_OCTEON        5  /* Cavium Networks Octeon.  */
+#define AFL_EXT_5900          6  /* MIPS R5900 instruction.  */
+#define AFL_EXT_4650          7  /* MIPS R4650 instruction.  */
+#define AFL_EXT_4010          8  /* LSI R4010 instruction.  */
+#define AFL_EXT_4100          9  /* NEC VR4100 instruction.  */
+#define AFL_EXT_3900         10  /* Toshiba R3900 instruction.  */
+#define AFL_EXT_10000        11  /* MIPS R10000 instruction.  */
+#define AFL_EXT_SB1          12  /* Broadcom SB-1 instruction.  */
+#define AFL_EXT_4111         13  /* NEC VR4111/VR4181 instruction.  */
+#define AFL_EXT_4120         14  /* NEC VR4120 instruction.  */
+#define AFL_EXT_5400         15  /* NEC VR5400 instruction.  */
+#define AFL_EXT_5500         16  /* NEC VR5500 instruction.  */
+#define AFL_EXT_LOONGSON_2E  17  /* ST Microelectronics Loongson 2E.  */
+#define AFL_EXT_LOONGSON_2F  18  /* ST Microelectronics Loongson 2F.  */
+#define AFL_EXT_OCTEON3      19  /* Cavium Networks Octeon3.  */
+
+/* Masks for the flags1 word of an ABI flags structure.  */
+#define AFL_FLAGS1_ODDSPREG   1	 /* Uses odd single-precision registers.  */
+
+extern unsigned int bfd_mips_isa_ext (bfd *);
 
 
 /* Object attribute tags.  */
@@ -1135,6 +1263,9 @@ enum
 
   /* Floating-point ABI used by this object file.  */
   Tag_GNU_MIPS_ABI_FP = 4,
+
+  /* MSA ABI used by this object file.  */
+  Tag_GNU_MIPS_ABI_MSA = 8,
 };
 
 /* Object attribute values.  */
@@ -1155,7 +1286,24 @@ enum
   Val_GNU_MIPS_ABI_FP_SOFT = 3,
 
   /* Using -mips32r2 -mfp64.  */
-  Val_GNU_MIPS_ABI_FP_64 = 4,
+  Val_GNU_MIPS_ABI_FP_OLD_64 = 4,
+
+  /* Using -mfpxx */
+  Val_GNU_MIPS_ABI_FP_XX = 5,
+
+  /* Using -mips32r2 -mfp64.  */
+  Val_GNU_MIPS_ABI_FP_64 = 6,
+
+  /* Using -mips32r2 -mfp64 -mno-odd-spreg.  */
+  Val_GNU_MIPS_ABI_FP_64A = 7,
+
+  /* Values defined for Tag_GNU_MIPS_ABI_MSA.  */
+
+  /* Not tagged or not using any ABIs affected by the differences.  */
+  Val_GNU_MIPS_ABI_MSA_ANY = 0,
+
+  /* Using 128-bit MSA.  */
+  Val_GNU_MIPS_ABI_MSA_128 = 1,
 };
 
 #endif /* _ELF_MIPS_H */
Index: include/elf/nds32.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ include/elf/nds32.h	2014-12-01 14:29:02.000000000 +0100
@@ -0,0 +1,299 @@
+/* NDS32 ELF support for BFD.
+   Copyright (C) 2012-2014 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#ifndef _ELF_NDS32_H
+#define _ELF_NDS32_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_nds32_reloc_type)
+  RELOC_NUMBER (R_NDS32_NONE, 0)
+  /* REL relocations.  */
+  RELOC_NUMBER (R_NDS32_16, 1)
+  RELOC_NUMBER (R_NDS32_32, 2)
+  RELOC_NUMBER (R_NDS32_20, 3)
+  RELOC_NUMBER (R_NDS32_9_PCREL, 4)
+  RELOC_NUMBER (R_NDS32_15_PCREL, 5)
+  RELOC_NUMBER (R_NDS32_17_PCREL, 6)
+  RELOC_NUMBER (R_NDS32_25_PCREL, 7)
+  RELOC_NUMBER (R_NDS32_HI20, 8)
+  RELOC_NUMBER (R_NDS32_LO12S3, 9)
+  RELOC_NUMBER (R_NDS32_LO12S2, 10)
+  RELOC_NUMBER (R_NDS32_LO12S1, 11)
+  RELOC_NUMBER (R_NDS32_LO12S0, 12)
+  RELOC_NUMBER (R_NDS32_SDA15S3, 13)
+  RELOC_NUMBER (R_NDS32_SDA15S2, 14)
+  RELOC_NUMBER (R_NDS32_SDA15S1, 15)
+  RELOC_NUMBER (R_NDS32_SDA15S0, 16)
+  RELOC_NUMBER (R_NDS32_GNU_VTINHERIT, 17)
+  RELOC_NUMBER (R_NDS32_GNU_VTENTRY, 18)
+
+  /* RELA relocations.  */
+  RELOC_NUMBER (R_NDS32_16_RELA, 19)
+  RELOC_NUMBER (R_NDS32_32_RELA, 20)
+  RELOC_NUMBER (R_NDS32_20_RELA, 21)
+  RELOC_NUMBER (R_NDS32_9_PCREL_RELA, 22)
+  RELOC_NUMBER (R_NDS32_15_PCREL_RELA, 23)
+  RELOC_NUMBER (R_NDS32_17_PCREL_RELA, 24)
+  RELOC_NUMBER (R_NDS32_25_PCREL_RELA, 25)
+  RELOC_NUMBER (R_NDS32_HI20_RELA, 26)
+  RELOC_NUMBER (R_NDS32_LO12S3_RELA, 27)
+  RELOC_NUMBER (R_NDS32_LO12S2_RELA, 28)
+  RELOC_NUMBER (R_NDS32_LO12S1_RELA, 29)
+  RELOC_NUMBER (R_NDS32_LO12S0_RELA, 30)
+  RELOC_NUMBER (R_NDS32_SDA15S3_RELA, 31)
+  RELOC_NUMBER (R_NDS32_SDA15S2_RELA, 32)
+  RELOC_NUMBER (R_NDS32_SDA15S1_RELA, 33)
+  RELOC_NUMBER (R_NDS32_SDA15S0_RELA, 34)
+  RELOC_NUMBER (R_NDS32_RELA_GNU_VTINHERIT, 35)
+  RELOC_NUMBER (R_NDS32_RELA_GNU_VTENTRY, 36)
+
+  RELOC_NUMBER (R_NDS32_GOT20, 37)
+  RELOC_NUMBER (R_NDS32_25_PLTREL, 38)
+  RELOC_NUMBER (R_NDS32_COPY, 39)
+  RELOC_NUMBER (R_NDS32_GLOB_DAT, 40)
+  RELOC_NUMBER (R_NDS32_JMP_SLOT, 41)
+  RELOC_NUMBER (R_NDS32_RELATIVE, 42)
+  RELOC_NUMBER (R_NDS32_GOTOFF, 43)
+  RELOC_NUMBER (R_NDS32_GOTPC20, 44)
+  RELOC_NUMBER (R_NDS32_GOT_HI20, 45)
+  RELOC_NUMBER (R_NDS32_GOT_LO12, 46)
+  RELOC_NUMBER (R_NDS32_GOTPC_HI20, 47)
+  RELOC_NUMBER (R_NDS32_GOTPC_LO12, 48)
+  RELOC_NUMBER (R_NDS32_GOTOFF_HI20, 49)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO12, 50)
+  RELOC_NUMBER (R_NDS32_INSN16, 51)
+  RELOC_NUMBER (R_NDS32_LABEL, 52)
+  RELOC_NUMBER (R_NDS32_LONGCALL1, 53)
+  RELOC_NUMBER (R_NDS32_LONGCALL2, 54)
+  RELOC_NUMBER (R_NDS32_LONGCALL3, 55)
+  RELOC_NUMBER (R_NDS32_LONGJUMP1, 56)
+  RELOC_NUMBER (R_NDS32_LONGJUMP2, 57)
+  RELOC_NUMBER (R_NDS32_LONGJUMP3, 58)
+  RELOC_NUMBER (R_NDS32_LOADSTORE, 59)
+  RELOC_NUMBER (R_NDS32_9_FIXED_RELA, 60)
+  RELOC_NUMBER (R_NDS32_15_FIXED_RELA, 61)
+  RELOC_NUMBER (R_NDS32_17_FIXED_RELA, 62)
+  RELOC_NUMBER (R_NDS32_25_FIXED_RELA, 63)
+  RELOC_NUMBER (R_NDS32_PLTREL_HI20, 64)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_PLTREL_LO12, 65)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_HI20, 66)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO12, 67)
+  RELOC_NUMBER (R_NDS32_SDA12S2_DP_RELA, 68)
+  RELOC_NUMBER (R_NDS32_SDA12S2_SP_RELA, 69)
+  RELOC_NUMBER (R_NDS32_LO12S2_DP_RELA, 70)
+  RELOC_NUMBER (R_NDS32_LO12S2_SP_RELA, 71)
+  RELOC_NUMBER (R_NDS32_LO12S0_ORI_RELA, 72)
+  RELOC_NUMBER (R_NDS32_SDA16S3_RELA, 73)
+  RELOC_NUMBER (R_NDS32_SDA17S2_RELA, 74)
+  RELOC_NUMBER (R_NDS32_SDA18S1_RELA, 75)
+  RELOC_NUMBER (R_NDS32_SDA19S0_RELA, 76)
+  RELOC_NUMBER (R_NDS32_DWARF2_OP1_RELA, 77)
+  RELOC_NUMBER (R_NDS32_DWARF2_OP2_RELA, 78)
+  RELOC_NUMBER (R_NDS32_DWARF2_LEB_RELA, 79)
+  RELOC_NUMBER (R_NDS32_UPDATE_TA_RELA, 80)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_9_PLTREL, 81)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO20, 82)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO15, 83)
+  RELOC_NUMBER (R_NDS32_PLT_GOTREL_LO19, 84)
+  RELOC_NUMBER (R_NDS32_GOT_LO15, 85)
+  RELOC_NUMBER (R_NDS32_GOT_LO19, 86)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO15, 87)
+  RELOC_NUMBER (R_NDS32_GOTOFF_LO19, 88)
+  RELOC_NUMBER (R_NDS32_GOT15S2_RELA, 89)
+  RELOC_NUMBER (R_NDS32_GOT17S2_RELA, 90)
+  RELOC_NUMBER (R_NDS32_5_RELA, 91)
+  RELOC_NUMBER (R_NDS32_10_UPCREL_RELA, 92)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_SDA_FP7U2_RELA, 93)
+  RELOC_NUMBER (R_NDS32_WORD_9_PCREL_RELA, 94)
+  RELOC_NUMBER (R_NDS32_25_ABS_RELA, 95)
+  RELOC_NUMBER (R_NDS32_17IFC_PCREL_RELA, 96)
+  RELOC_NUMBER (R_NDS32_10IFCU_PCREL_RELA, 97)
+  RELOC_NUMBER (R_NDS32_TLS_LE_HI20, 98)
+  RELOC_NUMBER (R_NDS32_TLS_LE_LO12, 99)
+  RELOC_NUMBER (R_NDS32_TLS_IE_HI20, 100)
+  RELOC_NUMBER (R_NDS32_TLS_IE_LO12S2, 101)
+  RELOC_NUMBER (R_NDS32_TLS_TPOFF, 102)
+  RELOC_NUMBER (R_NDS32_TLS_LE_20, 103)
+  RELOC_NUMBER (R_NDS32_TLS_LE_15S0, 104)
+  RELOC_NUMBER (R_NDS32_TLS_LE_15S1, 105)
+  RELOC_NUMBER (R_NDS32_TLS_LE_15S2, 106)
+  RELOC_NUMBER (R_NDS32_LONGCALL4, 107)
+  RELOC_NUMBER (R_NDS32_LONGCALL5, 108)
+  RELOC_NUMBER (R_NDS32_LONGCALL6, 109)
+  RELOC_NUMBER (R_NDS32_LONGJUMP4, 110)
+  RELOC_NUMBER (R_NDS32_LONGJUMP5, 111)
+  RELOC_NUMBER (R_NDS32_LONGJUMP6, 112)
+  RELOC_NUMBER (R_NDS32_LONGJUMP7, 113)
+
+  RELOC_NUMBER (R_NDS32_RELAX_ENTRY, 192)
+  RELOC_NUMBER (R_NDS32_GOT_SUFF, 193)
+  RELOC_NUMBER (R_NDS32_GOTOFF_SUFF, 194)
+  RELOC_NUMBER (R_NDS32_PLT_GOT_SUFF, 195)
+  RELOC_NUMBER (R_NDS32_MULCALL_SUFF, 196)	/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_PTR, 197)
+  RELOC_NUMBER (R_NDS32_PTR_COUNT, 198)
+  RELOC_NUMBER (R_NDS32_PTR_RESOLVED, 199)
+  RELOC_NUMBER (R_NDS32_PLTBLOCK, 200)		/* This is obsoleted.  */
+  RELOC_NUMBER (R_NDS32_RELAX_REGION_BEGIN, 201)
+  RELOC_NUMBER (R_NDS32_RELAX_REGION_END, 202)
+  RELOC_NUMBER (R_NDS32_MINUEND, 203)
+  RELOC_NUMBER (R_NDS32_SUBTRAHEND, 204)
+  RELOC_NUMBER (R_NDS32_DIFF8, 205)
+  RELOC_NUMBER (R_NDS32_DIFF16, 206)
+  RELOC_NUMBER (R_NDS32_DIFF32, 207)
+  RELOC_NUMBER (R_NDS32_DIFF_ULEB128, 208)
+  RELOC_NUMBER (R_NDS32_DATA, 209)
+  RELOC_NUMBER (R_NDS32_TRAN, 210)
+  RELOC_NUMBER (R_NDS32_TLS_LE_ADD, 211)
+  RELOC_NUMBER (R_NDS32_TLS_LE_LS, 212)
+  RELOC_NUMBER (R_NDS32_EMPTY, 213)
+
+END_RELOC_NUMBERS (R_NDS32_max)
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Processor specific flags for the ELF header e_flags field.
+
+   31   28 27		      8 7   4 3       0
+   ---------------------------------------------
+   | ARCH | CONFUGURAION FIELD | ABI | ELF_VER |
+   ---------------------------------------------  */
+
+/* Architechure definition.  */
+
+/* 4-bit (b31-b28) nds32 architecture field.
+   We can have up to 15 architectures; 0000 is for unknown.  */
+#define EF_NDS_ARCH				0xF0000000
+#define EF_NDS_ARCH_SHIFT			28
+/* There could be more architectures. For now, only n1 and n1h.  */
+#define E_NDS_ARCH_STAR_RESERVED		0x00000000
+#define E_NDS_ARCH_STAR_V1_0			0x10000000
+#define E_NDS_ARCH_STAR_V2_0			0x20000000
+#define E_NDS_ARCH_STAR_V3_0			0x30000000
+#define E_NDS_ARCH_STAR_V3_M			0x40000000
+#define E_NDS_ARCH_STAR_V0_9			0x90000000	/* Obsoleted.  */
+/* n1 code.  */
+#define E_N1_ARCH			E_NDS_ARCH_STAR_V0_9
+/* n1h code.  */
+#define E_N1H_ARCH			E_NDS_ARCH_STAR_V1_0
+
+
+/* Configuration field definitioans.  */
+#define EF_NDS_INST				0x0FFFFF00
+
+/* E_NDS_ARCH_STAR_V1_0 configuration fields.
+
+   E_NDS_ARCH_STAR_V2_0 configuration fields.
+   These are discarded in v2.
+     * E_NDS32_HAS_MFUSR_PC_INST	0x00000100
+     * E_NDS32_HAS_DIV_INST		0x00002000
+     * E_NDS32_HAS_NO_MAC_INST		0x00100000
+   These are added in v2.
+     * E_NDS32_HAS_DIV_DX_INST		0x00002000
+     * E_NDS32_HAS_MAC_DX_INST		0x00100000  */
+
+/* MFUSR rt, PC and correct ISYNC, MSYNC instructions.
+   Old N1213HC has no such instructions.  */
+#define E_NDS32_HAS_MFUSR_PC_INST		0x00000100 /* Reclaimed.  */
+#define E_NDS32_HAS_EX9_INST			0x00000100 /* v3, ELF 1.4.  */
+/* C/C++ performance extension instructions.  */
+#define E_NDS32_HAS_EXT_INST			0x00000200
+/* Performance extension set II instructions.  */
+#define E_NDS32_HAS_EXT2_INST			0x00000400
+/* Single precision Floating point processor instructions.  */
+#define E_NDS32_HAS_FPU_INST			0x00000800
+/* Audio instructions with 32-bit audio dx.lo register.  */
+#define E_NDS32_HAS_AUDIO_INST			0x00001000
+/* DIV instructions.  */
+#define E_NDS32_HAS_DIV_INST			0x00002000 /* Reclaimed.  */
+/* DIV instructions using d0/d1.  */
+#define E_NDS32_HAS_DIV_DX_INST			0x00002000 /* v2.  */
+/* 16-bit instructions.  */
+#define E_NDS32_HAS_16BIT_INST			0x00004000 /* Reclaimed.  */
+#define E_NDS32_HAS_IFC_INST			0x00004000 /* v3, ELF 1.4.  */
+/* String operation instructions.  */
+#define E_NDS32_HAS_STRING_INST			0x00008000
+/* Reduced register file.  */
+#define E_NDS32_HAS_REDUCED_REGS		0x00010000
+/* Video instructions.  */
+#define E_NDS32_HAS_VIDEO_INST			0x00020000 /* Reclaimed.  */
+#define E_NDS32_HAS_SATURATION_INST		0x00020000 /* v3, ELF 1.4.  */
+/* Encription instructions.  */
+#define E_NDS32_HAS_ENCRIPT_INST		0x00040000
+/* Doulbe Precision Floating point processor instructions.  */
+#define E_NDS32_HAS_FPU_DP_INST			0x00080000
+/* No MAC instruction used.  */
+#define E_NDS32_HAS_NO_MAC_INST			0x00100000 /* Reclaimed when V2/V3.  */
+/* MAC instruction using d0/d1.  */
+#define E_NDS32_HAS_MAC_DX_INST			0x00100000 /* v2.  */
+/* L2 cache instruction.  */
+#define E_NDS32_HAS_L2C_INST			0x00200000
+/* FPU registers configuration when FPU SP/DP presents; 0x00c00000.  */
+#define E_NDS32_FPU_REG_CONF_SHIFT		22
+#define E_NDS32_FPU_REG_CONF			(0x3 << E_NDS32_FPU_REG_CONF_SHIFT)
+#define E_NDS32_FPU_REG_8SP_4DP			0x0
+#define E_NDS32_FPU_REG_16SP_8DP		0x1
+#define E_NDS32_FPU_REG_32SP_16DP		0x2
+#define E_NDS32_FPU_REG_32SP_32DP		0x3
+/* FPU MAC instruction used.  */
+#define E_NDS32_HAS_FPU_MAC_INST		0x01000000
+/* <<<Empty Check>>>.  */
+#define E_NDS32_NULL				0x02000000
+/* PIC enabled.  */
+#define E_NDS32_HAS_PIC				0x04000000
+/* Use custom section.  */
+#define E_NDS32_HAS_CUSTOM_SEC			0x08000000
+
+/* 4-bit for ABI signature, allow up to 16 ABIs
+   0: for OLD ABI V0, phase out
+   1: for V1 , starting with V0 toolchain
+   2: for V2
+   3: for V2FP (fs0, fs1 as function parameter)
+   4: for AABI  */
+/* Only old N1213HC use V0.
+   New ABI is used due to return register is changed to r0 from r5.  */
+#define EF_NDS_ABI				0x000000F0
+#define EF_NDS_ABI_SHIFT			4
+#define E_NDS_ABI_V0				0x00000000
+#define E_NDS_ABI_V1				0x00000010
+#define E_NDS_ABI_V2				0x00000020
+#define E_NDS_ABI_V2FP				0x00000030
+#define E_NDS_ABI_AABI				0x00000040
+#define E_NDS_ABI_V2FP_PLUS			0x00000050
+
+/* This flag signifies the version of Andes ELF.
+   Some more information may exist somewhere which is TBD.  */
+#define EF_NDS32_ELF_VERSION			0x0000000F
+#define EF_NDS32_ELF_VERSION_SHIFT		0
+
+/* Andes ELF Version 1.3 and before.  */
+#define E_NDS32_ELF_VER_1_2			0x0
+/* Andes ELF Version 1.31.  */
+#define E_NDS32_ELF_VER_1_3			0x1
+/* Andes ELF Version 1.4. Change the way we fix .debug_* and .gcc_except_table.
+   Change three bit for EX9, IFC and SAT.  */
+#define E_NDS32_ELF_VER_1_4			0x2
+
+#endif
Index: include/elf/or1k.h
===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
+++ include/elf/or1k.h	2014-12-01 14:29:02.000000000 +0100
@@ -0,0 +1,65 @@
+/* Or1k ELF support for BFD.
+   Copyright 2001-2014 Free Software Foundation, Inc.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, see <http://www.gnu.org/licenses/> */
+
+#ifndef _ELF_OR1K_H
+#define _ELF_OR1K_H
+
+#include "elf/reloc-macros.h"
+
+/* Relocations.  */
+START_RELOC_NUMBERS (elf_or1k_reloc_type)
+  RELOC_NUMBER (R_OR1K_NONE,           0)
+  RELOC_NUMBER (R_OR1K_32,             1)
+  RELOC_NUMBER (R_OR1K_16,             2)
+  RELOC_NUMBER (R_OR1K_8,              3)
+  RELOC_NUMBER (R_OR1K_LO_16_IN_INSN,  4)
+  RELOC_NUMBER (R_OR1K_HI_16_IN_INSN,  5)
+  RELOC_NUMBER (R_OR1K_INSN_REL_26,    6)
+  RELOC_NUMBER (R_OR1K_GNU_VTENTRY,    7)
+  RELOC_NUMBER (R_OR1K_GNU_VTINHERIT,  8)
+  RELOC_NUMBER (R_OR1K_32_PCREL,       9)
+  RELOC_NUMBER (R_OR1K_16_PCREL,      10)
+  RELOC_NUMBER (R_OR1K_8_PCREL,       11)
+  RELOC_NUMBER (R_OR1K_GOTPC_HI16,    12)
+  RELOC_NUMBER (R_OR1K_GOTPC_LO16,    13)
+  RELOC_NUMBER (R_OR1K_GOT16,         14)
+  RELOC_NUMBER (R_OR1K_PLT26,         15)
+  RELOC_NUMBER (R_OR1K_GOTOFF_HI16,   16)
+  RELOC_NUMBER (R_OR1K_GOTOFF_LO16,   17)
+  RELOC_NUMBER (R_OR1K_COPY,          18)
+  RELOC_NUMBER (R_OR1K_GLOB_DAT,      19)
+  RELOC_NUMBER (R_OR1K_JMP_SLOT,      20)
+  RELOC_NUMBER (R_OR1K_RELATIVE,      21)
+  RELOC_NUMBER (R_OR1K_TLS_GD_HI16,   22)
+  RELOC_NUMBER (R_OR1K_TLS_GD_LO16,   23)
+  RELOC_NUMBER (R_OR1K_TLS_LDM_HI16,  24)
+  RELOC_NUMBER (R_OR1K_TLS_LDM_LO16,  25)
+  RELOC_NUMBER (R_OR1K_TLS_LDO_HI16,  26)
+  RELOC_NUMBER (R_OR1K_TLS_LDO_LO16,  27)
+  RELOC_NUMBER (R_OR1K_TLS_IE_HI16,   28)
+  RELOC_NUMBER (R_OR1K_TLS_IE_LO16,   29)
+  RELOC_NUMBER (R_OR1K_TLS_LE_HI16,   30)
+  RELOC_NUMBER (R_OR1K_TLS_LE_LO16,   31)
+  RELOC_NUMBER (R_OR1K_TLS_TPOFF,     32)
+  RELOC_NUMBER (R_OR1K_TLS_DTPOFF,    33)
+  RELOC_NUMBER (R_OR1K_TLS_DTPMOD,    34)
+END_RELOC_NUMBERS (R_OR1K_max)
+
+#define EF_OR1K_NODELAY (1UL << 0)
+
+#endif /* _ELF_OR1K_H */
Index: include/elf/ppc64.h
===================================================================
--- include/elf/ppc64.h.orig	2014-12-01 14:28:49.000000000 +0100
+++ include/elf/ppc64.h	2014-12-01 14:36:08.000000000 +0100
@@ -149,6 +149,10 @@ START_RELOC_NUMBERS (elf_ppc64_reloc_typ
   RELOC_NUMBER (R_PPC64_DTPREL16_HIGH,	   114)
   RELOC_NUMBER (R_PPC64_DTPREL16_HIGHA,	   115)
 
+/* Added for ELFv2.  */
+  RELOC_NUMBER (R_PPC64_REL24_NOTOC,	   116)
+  RELOC_NUMBER (R_PPC64_ADDR64_LOCAL,	   117)
+
 #ifndef RELOC_MACROS_GEN_FUNC
 /* Fake relocation only used internally by ld.  */
   RELOC_NUMBER (R_PPC64_LO_DS_OPT,	   128)
Index: include/elf/rl78.h
===================================================================
--- include/elf/rl78.h.orig	2014-12-01 14:29:02.000000000 +0100
+++ include/elf/rl78.h	2014-12-01 14:29:40.000000000 +0100
@@ -109,6 +109,7 @@ END_RELOC_NUMBERS (R_RL78_max)
 #define E_FLAG_RL78_G10			(1 << 2) /* CPU is missing register banks 1-3, so uses different ABI.  */
 
 /* These define the addend field of R_RL78_RH_RELAX relocations.  */
+#define RL78_RELAXA_MASK	0x000000f0	/* Mask for relax types */
 #define	RL78_RELAXA_BRA		0x00000010	/* Any type of branch (must be decoded).  */
 #define	RL78_RELAXA_ADDR16	0x00000020	/* addr16->sfr/saddr opportunity  */
 #define RL78_RELAXA_RNUM	0x0000000f	/* Number of associated relocations.  */
Index: include/elf/sparc.h
===================================================================
--- include/elf/sparc.h.orig	2014-12-01 14:28:49.000000000 +0100
+++ include/elf/sparc.h	2014-12-01 14:29:02.000000000 +0100
@@ -192,9 +192,19 @@ enum
 {
   /* 0-3 are generic.  */
   Tag_GNU_Sparc_HWCAPS = 4,
+  Tag_GNU_Sparc_HWCAPS2 = 8
 };
 
-/* These values match the AV_SPARC_* hwcap bits defined under Solaris.  */
+/* Generally speaking the ELF_SPARC_HWCAP_* and ELF_SPARC_HWCAP2_*
+   values match the AV_SPARC_* and AV2_SPARC_* bits respectively.
+
+   However Solaris 11 introduced a backwards-incompatible change
+   deprecating the RANDOM, TRANS and ASI_CACHE_SPARING bits in the
+   AT_SUNW_CAP_HW1 flags, reusing the bits for the unrelated hwcaps
+   FJATHHPC, FJDES and FJAES respectively.  In GNU/Linux we opted to
+   keep the old hwcaps in Tag_GNU_Sparc_HWCAPS and allocate bits for
+   FJATHHPC, FJDES and JFAES in Tag_GNU_Sparc_HWCAPS2.  */
+
 #define ELF_SPARC_HWCAP_MUL32	0x00000001 /* umul/umulcc/smul/smulcc insns */
 #define ELF_SPARC_HWCAP_DIV32	0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
 #define ELF_SPARC_HWCAP_FSMULD	0x00000004 /* 'fsmuld' insn */
@@ -228,4 +238,17 @@ enum
 #define ELF_SPARC_HWCAP_CBCOND	0x10000000 /* Compare and Branch insns */
 #define ELF_SPARC_HWCAP_CRC32C	0x20000000 /* CRC32C insn */
 
+#define ELF_SPARC_HWCAP2_FJATHPLUS 0x00000001 /* Fujitsu Athena+ */
+#define ELF_SPARC_HWCAP2_VIS3B     0x00000002 /* Subset of VIS3 present on sparc64 X+ */
+#define ELF_SPARC_HWCAP2_ADP       0x00000004 /* Application Data Protection */
+#define ELF_SPARC_HWCAP2_SPARC5    0x00000008 /* The 29 new fp and sub instructions */
+#define ELF_SPARC_HWCAP2_MWAIT     0x00000010 /* mwait instruction and load/monitor ASIs */
+#define ELF_SPARC_HWCAP2_XMPMUL    0x00000020 /* XOR multiple precision multiply */
+#define ELF_SPARC_HWCAP2_XMONT     0x00000040 /* XOR Montgomery mult/sqr instructions */
+#define ELF_SPARC_HWCAP2_NSEC      \
+                                   0x00000080 /* pause insn with support for nsec timings */
+#define ELF_SPARC_HWCAP2_FJATHHPC  0x00001000 /* Fujitsu HPC instrs */
+#define ELF_SPARC_HWCAP2_FJDES     0x00002000 /* Fujitsu DES instrs */
+#define ELF_SPARC_HWCAP2_FJAES     0x00010000 /* Fujitsu AES instrs */
+
 #endif /* _ELF_SPARC_H */
