From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Date: Mon, 21 May 2018 22:54:24 +0100
Subject: i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
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"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD).  To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.

Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present." (from x86/speculation: Add virtualized
speculative store bypass disable support in Linux).

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20180521215424.13520-4-berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
(cherry picked from commit cfeea0c021db6234c154dbc723730e81553924ff)
[BR: BSC#1092885 CVE-2018-3639]
Signed-off-by: Bruce Rogers <brogers@suse.com>
---
 target-i386/cpu.h     |  2 ++
 target-i386/kvm.c     | 17 +++++++++++++++--
 target-i386/machine.c | 20 ++++++++++++++++++++
 3 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 88e1fdc2cf9eb844de977541a175..7bcacd92b5966c3b4f6a70162e1c 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -326,6 +326,7 @@
 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
 #define MSR_TSC_ADJUST                  0x0000003b
 #define MSR_IA32_SPEC_CTRL              0x48
+#define MSR_VIRT_SSBD                   0xc001011f
 #define MSR_IA32_TSCDEADLINE            0x6e0
 
 #define MSR_P6_PERFCTR0                 0xc1
@@ -941,6 +942,7 @@ typedef struct CPUX86State {
     uint32_t smbase;
 
     uint64_t spec_ctrl;
+    uint64_t virt_ssbd;
 
     /* End of state preserved by INIT (dummy marker).  */
     struct {} end_init_save;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index f3f387f17a72a54512a4e6773d5b..9af5a8bbe6b8af062e9173e3aa17 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -96,6 +96,7 @@ static bool has_msr_hv_stimer;
 static bool has_msr_mtrr;
 static bool has_msr_xss;
 static bool has_msr_spec_ctrl;
+static bool has_msr_virt_ssbd;
 
 static bool has_msr_architectural_pmu;
 static uint32_t num_architectural_pmu_counters;
@@ -1045,6 +1046,10 @@ static int kvm_get_supported_msrs(KVMState *s)
                     has_msr_spec_ctrl = true;
                     continue;
                 }
+                if (kvm_msr_list->indices[i] == MSR_VIRT_SSBD) {
+                    has_msr_virt_ssbd = true;
+                    continue;
+                }
             }
         }
 
@@ -1550,6 +1555,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
     if (has_msr_spec_ctrl) {
         kvm_msr_entry_set(&msrs[n++], MSR_IA32_SPEC_CTRL, env->spec_ctrl);
     }
+    if (has_msr_virt_ssbd) {
+        kvm_msr_entry_set(&msrs[n++], MSR_VIRT_SSBD, env->virt_ssbd);
+    }
+
 #ifdef TARGET_X86_64
     if (lm_capable_kernel) {
         kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1977,8 +1986,9 @@ static int kvm_get_msrs(X86CPU *cpu)
     if (has_msr_spec_ctrl) {
         msrs[n++].index = MSR_IA32_SPEC_CTRL;
     }
-
-
+    if (has_msr_virt_ssbd) {
+        msrs[n++].index = MSR_VIRT_SSBD;
+    }
     if (!env->tsc_valid) {
         msrs[n++].index = MSR_IA32_TSC;
         env->tsc_valid = !runstate_is_running();
@@ -2296,6 +2306,9 @@ static int kvm_get_msrs(X86CPU *cpu)
         case MSR_IA32_SPEC_CTRL:
             env->spec_ctrl = msrs[i].data;
             break;
+        case MSR_VIRT_SSBD:
+            env->virt_ssbd = msrs[i].data;
+            break;
         }
     }
 
diff --git a/target-i386/machine.c b/target-i386/machine.c
index b5c2a09352fd6ebec57d895c18ad..7acef4847312ef5e7720a79110bc 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -909,6 +909,25 @@ static const VMStateDescription vmstate_spec_ctrl = {
     }
 };
 
+static bool virt_ssbd_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+
+    return env->virt_ssbd != 0;
+}
+
+static const VMStateDescription vmstate_msr_virt_ssbd = {
+    .name = "cpu/virt_ssbd",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = virt_ssbd_needed,
+    .fields = (VMStateField[]){
+        VMSTATE_UINT64(env.virt_ssbd, X86CPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 VMStateDescription vmstate_x86_cpu = {
     .name = "cpu",
     .version_id = 12,
@@ -1036,6 +1055,7 @@ VMStateDescription vmstate_x86_cpu = {
         &vmstate_pkru,
 #endif
         &vmstate_spec_ctrl,
+        &vmstate_msr_virt_ssbd,
         NULL
     }
 };
