From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: powerpc: Fix fatal SLB miss when restoring PPR
Git-commit: 0c4888ef1d8a8b82c29075ce7e257ff795af15c7
Patch-mainline: v3.13-rc1
References: bnc#853465 

When restoring the PPR value, we incorrectly access the thread structure
at a time where MSR:RI is clear, which means we cannot recover from nested
faults. However the thread structure isn't covered by the "bolted" SLB
entries and thus accessing can fault.

This fixes it by splitting the code so that the PPR value is loaded into
a GPR before MSR:RI is cleared.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Torsten Duwe <duwe@suse.de>

diff -Naurp linux.orig/arch/powerpc/kernel/entry_64.S linux/arch/powerpc/kernel/entry_64.S
--- linux.orig/arch/powerpc/kernel/entry_64.S	2013-11-27 22:29:26.000000000 -0500
+++ linux/arch/powerpc/kernel/entry_64.S	2013-11-28 01:57:42.000000000 -0500
@@ -647,6 +647,12 @@ FTR_SECTION_ELSE
 	ldarx	r4,0,r1
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
 
+	/* Load PPR from thread struct before we clear MSR:RI */
+BEGIN_FTR_SECTION
+	ld	r2,PACACURRENT(r13)
+	ld	r2,TASKTHREADPPR(r2)
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
+
 	/*
 	 * Clear RI before restoring r13.  If we are returning to
 	 * userspace and we take an exception after restoring r13,
@@ -662,8 +668,10 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_STCX_C
 	 */
 	andi.	r0,r3,MSR_PR
 	beq	1f
+BEGIN_FTR_SECTION
+	mtspr	SPRN_PPR,r2	/* Restore PPR */
+END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
 	ACCOUNT_CPU_USER_EXIT(r2, r4)
-	RESTORE_PPR(r2, r4)
 	REST_GPR(13, r1)
 1:
 	mtspr	SPRN_SRR1,r3
