From 7cbfd0653005d6c7a8f00d8ef5573b2976157780 Mon Sep 17 00:00:00 2001
From: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date: Wed, 31 Oct 2012 18:12:39 -0200
Subject: drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enable
Git-commit: 7cbfd0653005d6c7a8f00d8ef5573b2976157780
Patch-mainline: v3.8-rc1

This is just wrong. The lpt_program_iclkip should disable the PCH
pixel clocks (and yes, we plan to rename it later).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Michal Srb <msrb@suse.com>
---
 drivers/gpu/drm/i915/intel_display.c |    9 ---------
 1 files changed, 0 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22da6d1..88dd4c1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3181,15 +3181,6 @@ static void lpt_pch_enable(struct drm_crtc *crtc)
 	/* For PCH output, training FDI link */
 	dev_priv->display.fdi_link_train(crtc);
 
-	/* XXX: pch pll's can be enabled any time before we enable the PCH
-	 * transcoder, and we actually should do this to not upset any PCH
-	 * transcoder that already use the clock when we share it.
-	 *
-	 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
-	 * unconditionally resets the pll - we need that to have the right LVDS
-	 * enable sequence. */
-	ironlake_enable_pch_pll(intel_crtc);
-
 	lpt_program_iclkip(crtc);
 
 	/* set transcoder timing, panel must allow it */

