x86/spec-ctrl: CPUID/MSR definitions for L1D_FLUSH

This is part of XSA-273 / CVE-2018-3646.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>

--- a/docs/misc/xen-command-line.markdown
+++ b/docs/misc/xen-command-line.markdown
@@ -425,10 +425,10 @@ accounting for hardware capabilities as
 
 Currently accepted:
 
-The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`, `ssbd` are
-used by default if available and applicable.  They can be ignored,
-e.g. `no-ibrsb`, at which point Xen won't use them itself, and won't offer
-them to guests.
+The Speculation Control hardware features `ibrsb`, `stibp`, `ibpb`,
+`l1d-flush` and `ssbd` are used by default if available and applicable.  They can
+be ignored, e.g. `no-ibrsb`, at which point Xen won't use them itself, and
+won't offer them to guests.
 
 ### cpuid\_mask\_cpu (AMD only)
 > `= fam_0f_rev_c | fam_0f_rev_d | fam_0f_rev_e | fam_0f_rev_f | fam_0f_rev_g | fam_10_rev_b | fam_10_rev_c | fam_11_rev_b`
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -148,6 +148,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (edx) */
 #define X86_FEATURE_IBRSB       26 /* IBRS and IBPB support (used by Intel) */
 #define X86_FEATURE_STIBP       27 /* STIBP */
+#define X86_FEATURE_L1D_FLUSH   28 /* MSR_FLUSH_CMD and L1D flush. */
 #define X86_FEATURE_SSBD        31 /* MSR_SPEC_CTRL.SSBD available */
 
 #endif /* __LIBXC_CPUFEATURE_H */
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -369,6 +369,7 @@ static void xc_cpuid_hvm_policy(
                         bitmaskof(X86_FEATURE_FSGSBASE));
             regs[3] &= (bitmaskof(X86_FEATURE_IBRSB) |
                         bitmaskof(X86_FEATURE_STIBP) |
+                        bitmaskof(X86_FEATURE_L1D_FLUSH) |
                         bitmaskof(X86_FEATURE_SSBD));
         } else
             regs[1] = regs[3] = 0;
--- a/tools/libxl/libxl_cpuid.c
+++ b/tools/libxl/libxl_cpuid.c
@@ -160,6 +160,7 @@ int libxl_cpuid_parse_config(libxl_cpuid
         {"fpu",          0x00000001, NA, CPUID_REG_EDX,  0,  1},
         {"ibrsb",        0x00000007,  0, CPUID_REG_EDX, 26,  1},
         {"stibp",        0x00000007,  0, CPUID_REG_EDX, 27,  1},
+        {"l1d-flush",    0x00000007,  0, CPUID_REG_EDX, 28,  1},
         {"ssbd",         0x00000007,  0, CPUID_REG_EDX, 31,  1},
         {"topoext",      0x80000001, NA, CPUID_REG_ECX, 22,  1},
         {"tbm",          0x80000001, NA, CPUID_REG_ECX, 21,  1},
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -4369,6 +4369,8 @@ void hvm_cpuid(unsigned int input, unsig
             if ( !boot_cpu_has(X86_FEATURE_SC_MSR_HVM) )
                 *edx &= ~(cpufeat_mask(X86_FEATURE_IBRSB) |
                           cpufeat_mask(X86_FEATURE_SSBD));
+            if ( !boot_cpu_has(X86_FEATURE_L1D_FLUSH) )
+                *edx &= ~cpufeat_mask(X86_FEATURE_L1D_FLUSH);
 
             /*
              * Override STIBP to match IBRS.  Guests can safely use STIBP
--- a/xen/arch/x86/setup.c
+++ b/xen/arch/x86/setup.c
@@ -137,6 +137,11 @@ static int __init parse_xen_cpuid(const
             if ( !val )
                 setup_clear_cpu_cap(X86_FEATURE_STIBP);
         }
+        else if ( (val = parse_boolean("l1d-flush", s, ss)) >= 0 )
+        {
+            if ( !val )
+                setup_clear_cpu_cap(X86_FEATURE_L1D_FLUSH);
+        }
         else if ( (val = parse_boolean("ssbd", s, ss)) >= 0 )
         {
             if ( !val )
--- a/xen/arch/x86/spec_ctrl.c
+++ b/xen/arch/x86/spec_ctrl.c
@@ -249,9 +249,10 @@ static void __init print_details(enum in
     printk("Speculative mitigation facilities:\n");
 
     /* Hardware features which pertain to speculative mitigations. */
-    printk("  Hardware features:%s%s%s%s\n",
+    printk("  Hardware features:%s%s%s%s%s\n",
            (_7d0 & cpufeat_mask(X86_FEATURE_IBRSB)) ? " IBRS/IBPB" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_STIBP)) ? " STIBP"     : "",
+           (_7d0 & cpufeat_mask(X86_FEATURE_L1D_FLUSH)) ? " L1D_FLUSH" : "",
            (_7d0 & cpufeat_mask(X86_FEATURE_SSBD))  ? " SSBD"      : "",
            (e8b  & cpufeat_mask(X86_FEATURE_IBPB))  ? " IBPB"      : "");
 
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -816,6 +816,7 @@ void pv_cpuid(struct cpu_user_regs *regs
                 if ( !boot_cpu_has(X86_FEATURE_SC_MSR_PV) )
                     d &= ~(cpufeat_mask(X86_FEATURE_IBRSB) |
                            cpufeat_mask(X86_FEATURE_SSBD));
+                d &= ~cpufeat_mask(X86_FEATURE_L1D_FLUSH);
 
                 /*
                  * Override STIBP to match IBRS.  Guests can safely use STIBP
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -172,6 +172,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
 #define X86_FEATURE_IBRSB	(9*32+26) /* IBRS and IBPB support (used by Intel) */
 #define X86_FEATURE_STIBP	(9*32+27) /* STIBP */
+#define X86_FEATURE_L1D_FLUSH	(9*32+28) /* MSR_FLUSH_CMD and L1D flush. */
 #define X86_FEATURE_SSBD	(9*32+31) /* MSR_SPEC_CTRL.SSBD available */
 
 /* An alias of a feature we know is always going to be present. */
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -42,6 +42,9 @@
 
 #define MSR_ARCH_CAPABILITIES		0x0000010a
 
+#define MSR_FLUSH_CMD			0x0000010b
+#define FLUSH_CMD_L1D			(_AC(1, ULL) << 0)
+
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_A_PERFCTR0		0x000004c1
