// This file is automatically generated by rmconfig - DO NOT EDIT!
//
// Private HAL support for RPCSTRUCTURECOPY.
//
// Profile:  shipping-gpus-openrm
// Haldef:   rpcstructurecopy.def
// Template: templates/gt_eng_private.h
//

#ifndef _G_RPCSTRUCTURECOPY_PRIVATE_H_
#define _G_RPCSTRUCTURECOPY_PRIVATE_H_

#include "g_rpcstructurecopy_hal.h"


                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS   deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00;
Deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS   deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS   deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06;
Deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS   deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS   deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04;
Deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS   deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_P2P_CAPABILITY_PARAMS
Deserialize_VGPU_P2P_CAPABILITY_PARAMS   deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03;
Deserialize_VGPU_P2P_CAPABILITY_PARAMS   deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01;
Deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS   deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C;
Deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS   deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS   deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03;
Deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS   deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05;
Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v27_05;
Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v28_04;
Deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS   deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E;
Deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS   deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS   deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00;
Deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS   deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS   deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B;
Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS   deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13;
Deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS   deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_v29_05;
Deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS   deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05;
Deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS   deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v29_00;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES   deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07;
Deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES   deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_FB_GET_LTC_INFO_FOR_FBP
Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP   deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D;
Deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP   deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_STATIC_DATA
Deserialize_VGPU_STATIC_DATA       deserialize_VGPU_STATIC_DATA_v25_0E;
Deserialize_VGPU_STATIC_DATA       deserialize_VGPU_STATIC_DATA_v27_00;
Deserialize_VGPU_STATIC_DATA       deserialize_VGPU_STATIC_DATA_v27_01;
Deserialize_VGPU_STATIC_DATA       deserialize_VGPU_STATIC_DATA_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B;
Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS   deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00;
Deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS   deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS   deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01;
Deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS   deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_FIFO_GET_DEVICE_INFO_TABLE
Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE   deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07;
Deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE   deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS   deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A;
Deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS   deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:GPU_EXEC_SYSPIPE_INFO
Deserialize_GPU_EXEC_SYSPIPE_INFO   deserialize_GPU_EXEC_SYSPIPE_INFO_v26_01;
Deserialize_GPU_EXEC_SYSPIPE_INFO   deserialize_GPU_EXEC_SYSPIPE_INFO_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_BSP_GET_CAPS
Deserialize_VGPU_BSP_GET_CAPS      deserialize_VGPU_BSP_GET_CAPS_v25_00;
Deserialize_VGPU_BSP_GET_CAPS      deserialize_VGPU_BSP_GET_CAPS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08;
Deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS   deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:GPU_PARTITION_INFO
Deserialize_GPU_PARTITION_INFO     deserialize_GPU_PARTITION_INFO_v24_05;
Deserialize_GPU_PARTITION_INFO     deserialize_GPU_PARTITION_INFO_v28_02;
Deserialize_GPU_PARTITION_INFO     deserialize_GPU_PARTITION_INFO_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS   deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09;
Deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS   deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS   deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00;
Deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS   deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS   deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07;
Deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS   deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS   deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02;
Deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS   deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_STATIC_PROPERTIES
Deserialize_VGPU_STATIC_PROPERTIES   deserialize_VGPU_STATIC_PROPERTIES_v1B_01;
Deserialize_VGPU_STATIC_PROPERTIES   deserialize_VGPU_STATIC_PROPERTIES_v26_03;
Deserialize_VGPU_STATIC_PROPERTIES   deserialize_VGPU_STATIC_PROPERTIES_v29_03;
Deserialize_VGPU_STATIC_PROPERTIES   deserialize_VGPU_STATIC_PROPERTIES_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS   deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09;
Deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS   deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS   deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01;
Deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS   deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07;
Deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS   deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_FLA_GET_RANGE_PARAMS
Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS   deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18;
Deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS   deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS   deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F;
Deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS   deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06;
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02;
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v27_04;
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v28_01;
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v28_08;
Deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS   deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_CE_GET_CAPS_V2
Deserialize_VGPU_CE_GET_CAPS_V2    deserialize_VGPU_CE_GET_CAPS_V2_v24_09;
Deserialize_VGPU_CE_GET_CAPS_V2    deserialize_VGPU_CE_GET_CAPS_V2_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:VGPU_GET_LATENCY_BUFFER_SIZE
Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE   deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09;
Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE   deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v27_02;
Deserialize_VGPU_GET_LATENCY_BUFFER_SIZE   deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207

                                               // RPCSTRUCTURECOPY:NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS   deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00;
Deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS   deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB;  // TU10X, GA100, GA102, GA103, GA104, GA106, GA107, AD102, AD103, AD104, AD106, AD107, GH10X, GB100, GB102, GB10B, GB202, GB203, GB205, GB206, GB207






//
// RPCSTRUCTURECOPY's object-level *non-static* interface functions (static ones are below)
//



#if defined(RMCFG_ENGINE_SETUP)    // for use by hal init only





// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v03_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v12_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v15_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v15_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v16_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v18_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_0D(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_18(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1A_1F(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1B_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1B_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1C_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1C_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1D_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1D_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1E_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1E_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1F_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v1F_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v20_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v21_0A(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v21_0C(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v22_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v24_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v24_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v24_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v24_09(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_06(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_07(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_0B(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_0E(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v25_13(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v26_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v26_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v26_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v27_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v27_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v27_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v27_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v27_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v28_01(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v28_02(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v28_04(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v28_08(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v29_00(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v29_03(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}

// No enabled chips use this variant provider
static void rpcstructurecopy_iGrp_ipVersions_Install_v29_05(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
#if 0

    POBJGPU pGpu = pInfo->pGpu;
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pGpu += 0;
    pRpcstructurecopyHal += 0;


#endif // 
}




// the "_UNASSIGNED" function for all IP_VERSIONS dynamic interfaces
NV_STATUS iGrp_ipVersions_UNASSIGNED(void);


static NV_STATUS rpcstructurecopy_iGrp_ipVersions_Wrapup(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
    OBJRPCSTRUCTURECOPY *pRpcstructurecopy = (OBJRPCSTRUCTURECOPY *) pInfo->pDynamic;
    RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal = &pRpcstructurecopy->_hal;

    // avoid possible unused warnings
    pRpcstructurecopyHal += 0;

    // fixup per-interface overrides?
    if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS = deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_v03_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25060000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS = deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_v25_06;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x20040000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS = deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_v20_04;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25030000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_P2P_CAPABILITY_PARAMS = deserialize_VGPU_P2P_CAPABILITY_PARAMS_v25_03;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x22010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_v22_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x210C0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS = deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_v21_0C;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x15030000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS = deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_v15_03;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1F010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_v1F_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25050000, 0x2704FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v25_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x27050000, 0x2803FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v27_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x28040000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_v28_04;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x250E0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS = deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_v25_0E;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS = deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_v03_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x180B0000, 0x2512FFFF))
       pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS = deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v18_0B;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25130000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS = deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_v25_13;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x29050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_v29_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x24050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS = deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_v24_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x24070000, 0x28FFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v24_07;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x29000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_v29_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES = deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_v1A_07;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1B_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A0D0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP = deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_v1A_0D;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x250E0000, 0x26FFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA = deserialize_VGPU_STATIC_DATA_v25_0E;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x27000000, 0x2700FFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA = deserialize_VGPU_STATIC_DATA_v27_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x27010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA = deserialize_VGPU_STATIC_DATA_v27_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1E020000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_v1E_02;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x250B0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_v25_0B;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1D040000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_v1D_04;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1C060000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_v1C_06;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x03000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS = deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_v03_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x12010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS = deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_v12_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1D030000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_v1D_03;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_v1B_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE = deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_v1A_07;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x210A0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS = deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_v21_0A;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x26010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_GPU_EXEC_SYSPIPE_INFO = deserialize_GPU_EXEC_SYSPIPE_INFO_v26_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_BSP_GET_CAPS = deserialize_VGPU_BSP_GET_CAPS_v25_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1F080000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS = deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_v1F_08;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x24050000, 0x2801FFFF))
       pRpcstructurecopyHal->deserialize_GPU_PARTITION_INFO = deserialize_GPU_PARTITION_INFO_v24_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x28020000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_GPU_PARTITION_INFO = deserialize_GPU_PARTITION_INFO_v28_02;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1E090000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS = deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_v1E_09;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x16000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS = deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_v16_00;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_v1B_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A070000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS = deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_v1A_07;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1B050000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_v1B_05;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x15020000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS = deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_v15_02;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1B010000, 0x2602FFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES = deserialize_VGPU_STATIC_PROPERTIES_v1B_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x26030000, 0x2902FFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES = deserialize_VGPU_STATIC_PROPERTIES_v26_03;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x29030000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES = deserialize_VGPU_STATIC_PROPERTIES_v29_03;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1C090000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS = deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_v1C_09;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25010000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS = deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_v25_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25070000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS = deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_v25_07;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A180000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS = deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_v1A_18;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1A1F0000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS = deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_v1A_1F;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x24060000, 0x2601FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v24_06;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x26020000, 0x2703FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v26_02;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x27040000, 0x2800FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v27_04;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x28010000, 0x2807FFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v28_01;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x28080000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS = deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_v28_08;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x24090000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_CE_GET_CAPS_V2 = deserialize_VGPU_CE_GET_CAPS_V2_v24_09;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x1C090000, 0x2701FFFF))
       pRpcstructurecopyHal->deserialize_VGPU_GET_LATENCY_BUFFER_SIZE = deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v1C_09;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x27020000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_VGPU_GET_LATENCY_BUFFER_SIZE = deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_v27_02;
    if (IsIPVersionInRange(pRpcstructurecopy, 0x25000000, 0xFFFFFFFF))
       pRpcstructurecopyHal->deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS = deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_v25_00;

    // Verify each 'dynamically set' interface was actually set

#define _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(_pHalFn) \
           NV_ASSERT_OR_RETURN_PRECOMP(_pHalFn != (void *) iGrp_ipVersions_UNASSIGNED, NV_ERR_NOT_SUPPORTED)

    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_P2P_CAPABILITY_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_STATIC_DATA);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_GPU_EXEC_SYSPIPE_INFO);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_BSP_GET_CAPS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_GPU_PARTITION_INFO);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_STATIC_PROPERTIES);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_CE_GET_CAPS_V2);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_VGPU_GET_LATENCY_BUFFER_SIZE);
    _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE(pRpcstructurecopyHal->deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS);

#undef _RPCSTRUCTURECOPY_HAL_VERIFY_INTERFACE

    return NV_OK;
}


static NV_STATUS rpcstructurecopy_iGrp_ipVersions_getInfo(IGRP_IP_VERSIONS_TABLE_INFO *pInfo)
{
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v03_00[] = {
        { 0x03000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v12_01[] = {
        { 0x12010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v15_02[] = {
        { 0x15020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v15_03[] = {
        { 0x15030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v16_00[] = {
        { 0x16000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v18_0B[] = {
        { 0x180B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_07[] = {
        { 0x1A070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_0D[] = {
        { 0x1A0D0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_18[] = {
        { 0x1A180000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1A_1F[] = {
        { 0x1A1F0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1B_01[] = {
        { 0x1B010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1B_05[] = {
        { 0x1B050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1C_06[] = {
        { 0x1C060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1C_09[] = {
        { 0x1C090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1D_03[] = {
        { 0x1D030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1D_04[] = {
        { 0x1D040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1E_02[] = {
        { 0x1E020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1E_09[] = {
        { 0x1E090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1F_01[] = {
        { 0x1F010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v1F_08[] = {
        { 0x1F080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v20_04[] = {
        { 0x20040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v21_0A[] = {
        { 0x210A0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v21_0C[] = {
        { 0x210C0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v22_01[] = {
        { 0x22010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_05[] = {
        { 0x24050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_06[] = {
        { 0x24060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_07[] = {
        { 0x24070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v24_09[] = {
        { 0x24090000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_00[] = {
        { 0x25000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_01[] = {
        { 0x25010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_03[] = {
        { 0x25030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_05[] = {
        { 0x25050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_06[] = {
        { 0x25060000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_07[] = {
        { 0x25070000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_0B[] = {
        { 0x250B0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_0E[] = {
        { 0x250E0000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v25_13[] = {
        { 0x25130000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v26_01[] = {
        { 0x26010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v26_02[] = {
        { 0x26020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v26_03[] = {
        { 0x26030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v27_00[] = {
        { 0x27000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v27_01[] = {
        { 0x27010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v27_02[] = {
        { 0x27020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v27_04[] = {
        { 0x27040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v27_05[] = {
        { 0x27050000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v28_01[] = {
        { 0x28010000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v28_02[] = {
        { 0x28020000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v28_04[] = {
        { 0x28040000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v28_08[] = {
        { 0x28080000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v29_00[] = {
        { 0x29000000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v29_03[] = {
        { 0x29030000, 0xFFFFFFFF, },          // 
    };
    static const IGRP_IP_VERSION_RANGE  RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_v29_05[] = {
        { 0x29050000, 0xFFFFFFFF, },          // 
    };

#define _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v) \
    { RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_##v, NV_ARRAY_ELEMENTS(RPCSTRUCTURECOPY_IGRP_IP_VERSIONS_RANGES_##v), rpcstructurecopy_iGrp_ipVersions_Install_##v, }

    static const IGRP_IP_VERSIONS_ENTRY rpcstructurecopy_iGrp_ipVersions_table[] = {
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v03_00),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v12_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v15_02),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v15_03),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v16_00),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v18_0B),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_07),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_0D),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_18),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1A_1F),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1B_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1B_05),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1C_06),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1C_09),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1D_03),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1D_04),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1E_02),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1E_09),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1F_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v1F_08),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v20_04),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v21_0A),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v21_0C),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v22_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_05),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_06),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_07),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v24_09),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_00),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_03),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_05),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_06),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_07),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_0B),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_0E),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v25_13),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v26_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v26_02),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v26_03),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v27_00),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v27_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v27_02),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v27_04),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v27_05),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v28_01),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v28_02),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v28_04),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v28_08),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v29_00),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v29_03),    // 
        _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT(v29_05),    // 
    };

#undef _RPCSTRUCTURECOPY_HAL_IGRP_ENTRY_INIT

    pInfo->pTable         = rpcstructurecopy_iGrp_ipVersions_table;
    pInfo->numEntries     = NV_ARRAY_ELEMENTS(rpcstructurecopy_iGrp_ipVersions_table);
    pInfo->ifacesWrapupFn = rpcstructurecopy_iGrp_ipVersions_Wrapup;

    return NV_OK;
}


//
// Setup RPCSTRUCTURECOPY's hal interface function pointers
//

#if defined(RMCFG_HAL_SETUP_TU102)

static void rpcstructurecopyHalIfacesSetup_TU102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // TU102's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_TU102 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_TU102

    // init TU102's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_TU102;
}

#endif  // TU10X or TU102

#if defined(RMCFG_HAL_SETUP_TU104)

static void rpcstructurecopyHalIfacesSetup_TU104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal);   // TU104 interfaces identical to TU102
}

#endif  // TU10X or TU104

#if defined(RMCFG_HAL_SETUP_TU106)

static void rpcstructurecopyHalIfacesSetup_TU106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal);   // TU106 interfaces identical to TU102
}

#endif  // TU10X or TU106

#if defined(RMCFG_HAL_SETUP_TU116)

static void rpcstructurecopyHalIfacesSetup_TU116(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal);   // TU116 interfaces identical to TU102
}

#endif  // TU10X or TU116

#if defined(RMCFG_HAL_SETUP_TU117)

static void rpcstructurecopyHalIfacesSetup_TU117(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_TU102(pRpcstructurecopyHal);   // TU117 interfaces identical to TU102
}

#endif  // TU10X or TU117

#if defined(RMCFG_HAL_SETUP_GA100)

static void rpcstructurecopyHalIfacesSetup_GA100(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // GA100's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GA100 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_GA100

    // init GA100's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GA100;
}

#endif  // GA10X or GA100

#if defined(RMCFG_HAL_SETUP_GA102)

static void rpcstructurecopyHalIfacesSetup_GA102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal);   // GA102 interfaces identical to GA100
}

#endif  // GA10X or GA102

#if defined(RMCFG_HAL_SETUP_GA103)

static void rpcstructurecopyHalIfacesSetup_GA103(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal);   // GA103 interfaces identical to GA100
}

#endif  // GA10X or GA103

#if defined(RMCFG_HAL_SETUP_GA104)

static void rpcstructurecopyHalIfacesSetup_GA104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal);   // GA104 interfaces identical to GA100
}

#endif  // GA10X or GA104

#if defined(RMCFG_HAL_SETUP_GA106)

static void rpcstructurecopyHalIfacesSetup_GA106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal);   // GA106 interfaces identical to GA100
}

#endif  // GA10X or GA106

#if defined(RMCFG_HAL_SETUP_GA107)

static void rpcstructurecopyHalIfacesSetup_GA107(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GA100(pRpcstructurecopyHal);   // GA107 interfaces identical to GA100
}

#endif  // GA10X or GA107

#if defined(RMCFG_HAL_SETUP_AD102)

static void rpcstructurecopyHalIfacesSetup_AD102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // AD102's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_AD102 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_AD102

    // init AD102's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_AD102;
}

#endif  // AD10X or AD102

#if defined(RMCFG_HAL_SETUP_AD103)

static void rpcstructurecopyHalIfacesSetup_AD103(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal);   // AD103 interfaces identical to AD102
}

#endif  // AD10X or AD103

#if defined(RMCFG_HAL_SETUP_AD104)

static void rpcstructurecopyHalIfacesSetup_AD104(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal);   // AD104 interfaces identical to AD102
}

#endif  // AD10X or AD104

#if defined(RMCFG_HAL_SETUP_AD106)

static void rpcstructurecopyHalIfacesSetup_AD106(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal);   // AD106 interfaces identical to AD102
}

#endif  // AD10X or AD106

#if defined(RMCFG_HAL_SETUP_AD107)

static void rpcstructurecopyHalIfacesSetup_AD107(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_AD102(pRpcstructurecopyHal);   // AD107 interfaces identical to AD102
}

#endif  // AD10X or AD107

#if defined(RMCFG_HAL_SETUP_GH100)

static void rpcstructurecopyHalIfacesSetup_GH100(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // GH100's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GH100 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_GH100

    // init GH100's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GH100;
}

#endif  // GH10X or GH100

#if defined(RMCFG_HAL_SETUP_GB100)

static void rpcstructurecopyHalIfacesSetup_GB100(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // GB100's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GB100 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_GB100

    // init GB100's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GB100;
}

#endif  // GB10X or GB100

#if defined(RMCFG_HAL_SETUP_GB102)

static void rpcstructurecopyHalIfacesSetup_GB102(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB100(pRpcstructurecopyHal);   // GB102 interfaces identical to GB100
}

#endif  // GB10X or GB102

#if defined(RMCFG_HAL_SETUP_GB10B)

static void rpcstructurecopyHalIfacesSetup_GB10B(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB100(pRpcstructurecopyHal);   // GB10B interfaces identical to GB100
}

#endif  // GB10X or GB10B

#if defined(RMCFG_HAL_SETUP_GB202)

static void rpcstructurecopyHalIfacesSetup_GB202(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{

    // GB202's RPCSTRUCTURECOPY hal interface function pointer block
    static const RPCSTRUCTURECOPY_HAL_IFACES rpcstructurecopyHalIfacesInitStruct_GB202 =
    {
        deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_FB_GET_FB_REGION_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_MEMSYS_GET_STATIC_CONFIG_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS
        deserialize_VGPU_P2P_CAPABILITY_PARAMS_STUB,   // deserialize_VGPU_P2P_CAPABILITY_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS
        deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_STUB,   // deserialize_NVA080_CTRL_VGPU_GET_CONFIG_PARAMS
        deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS_STUB,   // deserialize_NV2080_CTRL_FB_GET_LTC_INFO_FOR_FBP_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_GET_DEVICE_INFO_TABLE_PARAMS
        deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_BIOS_GET_SKU_INFO_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_GID_INFO_PARAMS
        deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS_STUB,   // deserialize_NV90E6_CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_CCU_SAMPLE_INFO_PARAMS
        deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS_STUB,   // deserialize_NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS
        deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES_STUB,   // deserialize_VGPU_FB_GET_DYNAMIC_BLACKLISTED_PAGES
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP_STUB,   // deserialize_VGPU_FB_GET_LTC_INFO_FOR_FBP
        deserialize_VGPU_STATIC_DATA_STUB,       // deserialize_VGPU_STATIC_DATA
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS
        deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS_STUB,   // deserialize_NV0000_CTRL_SYSTEM_GET_VGX_SYSTEM_INFO_PARAMS
        deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS
        deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE_STUB,   // deserialize_VGPU_FIFO_GET_DEVICE_INFO_TABLE
        deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS
        deserialize_GPU_EXEC_SYSPIPE_INFO_STUB,   // deserialize_GPU_EXEC_SYSPIPE_INFO
        deserialize_VGPU_BSP_GET_CAPS_STUB,      // deserialize_VGPU_BSP_GET_CAPS
        deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS
        deserialize_GPU_PARTITION_INFO_STUB,     // deserialize_GPU_PARTITION_INFO
        deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_STATIC_INTR_TABLE_PARAMS
        deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS_STUB,   // deserialize_NV2080_CTRL_MC_GET_ENGINE_NOTIFICATION_INTR_VECTORS_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS
        deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS_STUB,   // deserialize_NV9096_CTRL_GET_ZBC_CLEAR_TABLE_SIZE_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS
        deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS_STUB,   // deserialize_NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS
        deserialize_VGPU_STATIC_PROPERTIES_STUB,   // deserialize_VGPU_STATIC_PROPERTIES
        deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS_STUB,   // deserialize_NV2080_CTRL_BUS_GET_INFO_V2_PARAMS
        deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS
        deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_STUB,   // deserialize_NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS
        deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS_STUB,   // deserialize_NV2080_CTRL_FLA_GET_RANGE_PARAMS
        deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_STUB,   // deserialize_NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS
        deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_STUB,   // deserialize_NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS
        deserialize_VGPU_CE_GET_CAPS_V2_STUB,    // deserialize_VGPU_CE_GET_CAPS_V2
        deserialize_VGPU_GET_LATENCY_BUFFER_SIZE_STUB,   // deserialize_VGPU_GET_LATENCY_BUFFER_SIZE
        deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS_STUB,   // deserialize_NV0080_CTRL_MSENC_GET_CAPS_V2_PARAMS
        rpcstructurecopy_iGrp_ipVersions_getInfo,   // rpcstructurecopy_iGrp_ipVersions_getInfo

    };  // rpcstructurecopyHalIfacesInitStruct_GB202

    // init GB202's RPCSTRUCTURECOPY function ptrs using the init struct above
    *pRpcstructurecopyHal = rpcstructurecopyHalIfacesInitStruct_GB202;
}

#endif  // GB20X or GB202

#if defined(RMCFG_HAL_SETUP_GB203)

static void rpcstructurecopyHalIfacesSetup_GB203(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB202(pRpcstructurecopyHal);   // GB203 interfaces identical to GB202
}

#endif  // GB20X or GB203

#if defined(RMCFG_HAL_SETUP_GB205)

static void rpcstructurecopyHalIfacesSetup_GB205(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB202(pRpcstructurecopyHal);   // GB205 interfaces identical to GB202
}

#endif  // GB20X or GB205

#if defined(RMCFG_HAL_SETUP_GB206)

static void rpcstructurecopyHalIfacesSetup_GB206(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB202(pRpcstructurecopyHal);   // GB206 interfaces identical to GB202
}

#endif  // GB20X or GB206

#if defined(RMCFG_HAL_SETUP_GB207)

static void rpcstructurecopyHalIfacesSetup_GB207(RPCSTRUCTURECOPY_HAL_IFACES *pRpcstructurecopyHal)
{
    rpcstructurecopyHalIfacesSetup_GB202(pRpcstructurecopyHal);   // GB207 interfaces identical to GB202
}

#endif  // GB20X or GB207





#endif  // RMCFG_ENGINE_SETUP



// Were any _MOCK interfaces generated into g_rpcstructurecopy_private.h ?
#define RPCSTRUCTURECOPY_MOCK_FUNCTIONS_GENERATED 0


#endif  // _G_RPCSTRUCTURECOPY_PRIVATE_H_
